mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 18:56:15 +09:00
676ae068d9
Kill off ehci-core.h It was used to specify some static controller data. To support more than one controller being active at any time we have to carry the controller data ourselfes. Change the ehci interface accordingly. NOTE: OMAP implemented the ehci stuff a bit backwards and should be fixed to do the same thing as other platforms. But the change for now is at least compile clean. Signed-off-by: Lucas Stach <dev@lynxeye.de> Reviewed-by: Marek Vasut <marex@denx.de>
161 lines
4.6 KiB
C
161 lines
4.6 KiB
C
/*
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* Freescale i.MX28 USB Host driver
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/regs-common.h>
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#include <asm/arch/regs-base.h>
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#include <asm/arch/regs-clkctrl-mx28.h>
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#include <asm/arch/regs-usb.h>
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#include <asm/arch/regs-usbphy.h>
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#include "ehci.h"
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#if (CONFIG_EHCI_MXS_PORT != 0) && (CONFIG_EHCI_MXS_PORT != 1)
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#error "MXS EHCI: Invalid port selected!"
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#endif
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#ifndef CONFIG_EHCI_MXS_PORT
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#error "MXS EHCI: Please define correct port using CONFIG_EHCI_MXS_PORT!"
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#endif
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static struct ehci_mxs {
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struct mxs_usb_regs *usb_regs;
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struct mxs_usbphy_regs *phy_regs;
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} ehci_mxs;
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int mxs_ehci_get_port(struct ehci_mxs *mxs_usb, int port)
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{
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uint32_t usb_base, phy_base;
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switch (port) {
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case 0:
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usb_base = MXS_USBCTRL0_BASE;
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phy_base = MXS_USBPHY0_BASE;
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break;
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case 1:
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usb_base = MXS_USBCTRL1_BASE;
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phy_base = MXS_USBPHY1_BASE;
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break;
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default:
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printf("CONFIG_EHCI_MXS_PORT (port = %d)\n", port);
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return -1;
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}
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mxs_usb->usb_regs = (struct mxs_usb_regs *)usb_base;
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mxs_usb->phy_regs = (struct mxs_usbphy_regs *)phy_base;
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return 0;
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}
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/* This DIGCTL register ungates clock to USB */
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#define HW_DIGCTL_CTRL 0x8001c000
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#define HW_DIGCTL_CTRL_USB0_CLKGATE (1 << 2)
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#define HW_DIGCTL_CTRL_USB1_CLKGATE (1 << 16)
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int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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int ret;
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uint32_t usb_base, cap_base;
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struct mxs_register_32 *digctl_ctrl =
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(struct mxs_register_32 *)HW_DIGCTL_CTRL;
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struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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ret = mxs_ehci_get_port(&ehci_mxs, CONFIG_EHCI_MXS_PORT);
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if (ret)
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return ret;
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/* Reset the PHY block */
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writel(USBPHY_CTRL_SFTRST, &ehci_mxs.phy_regs->hw_usbphy_ctrl_set);
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udelay(10);
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writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE,
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&ehci_mxs.phy_regs->hw_usbphy_ctrl_clr);
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/* Enable USB clock */
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writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER,
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&clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
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writel(CLKCTRL_PLL1CTRL0_EN_USB_CLKS | CLKCTRL_PLL1CTRL0_POWER,
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&clkctrl_regs->hw_clkctrl_pll1ctrl0_set);
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writel(HW_DIGCTL_CTRL_USB0_CLKGATE | HW_DIGCTL_CTRL_USB1_CLKGATE,
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&digctl_ctrl->reg_clr);
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/* Start USB PHY */
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writel(0, &ehci_mxs.phy_regs->hw_usbphy_pwd);
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/* Enable UTMI+ Level 2 and Level 3 compatibility */
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writel(USBPHY_CTRL_ENUTMILEVEL3 | USBPHY_CTRL_ENUTMILEVEL2 | 1,
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&ehci_mxs.phy_regs->hw_usbphy_ctrl_set);
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usb_base = ((uint32_t)ehci_mxs.usb_regs) + 0x100;
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*hccr = (struct ehci_hccr *)usb_base;
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cap_base = ehci_readl(&(*hccr)->cr_capbase);
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*hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
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return 0;
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}
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int ehci_hcd_stop(int index)
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{
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int ret;
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uint32_t usb_base, cap_base, tmp;
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struct mxs_register_32 *digctl_ctrl =
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(struct mxs_register_32 *)HW_DIGCTL_CTRL;
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struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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struct ehci_hccr *hccr;
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struct ehci_hcor *hcor;
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ret = mxs_ehci_get_port(&ehci_mxs, CONFIG_EHCI_MXS_PORT);
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if (ret)
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return ret;
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/* Stop the USB port */
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usb_base = ((uint32_t)ehci_mxs.usb_regs) + 0x100;
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hccr = (struct ehci_hccr *)usb_base;
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cap_base = ehci_readl(&hccr->cr_capbase);
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hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
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tmp = ehci_readl(&hcor->or_usbcmd);
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tmp &= ~CMD_RUN;
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ehci_writel(tmp, &hcor->or_usbcmd);
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/* Disable the PHY */
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tmp = USBPHY_PWD_RXPWDRX | USBPHY_PWD_RXPWDDIFF |
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USBPHY_PWD_RXPWD1PT1 | USBPHY_PWD_RXPWDENV |
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USBPHY_PWD_TXPWDV2I | USBPHY_PWD_TXPWDIBIAS |
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USBPHY_PWD_TXPWDFS;
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writel(tmp, &ehci_mxs.phy_regs->hw_usbphy_pwd);
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/* Disable USB clock */
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writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS,
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&clkctrl_regs->hw_clkctrl_pll0ctrl0_clr);
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writel(CLKCTRL_PLL1CTRL0_EN_USB_CLKS,
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&clkctrl_regs->hw_clkctrl_pll1ctrl0_clr);
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/* Gate off the USB clock */
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writel(HW_DIGCTL_CTRL_USB0_CLKGATE | HW_DIGCTL_CTRL_USB1_CLKGATE,
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&digctl_ctrl->reg_set);
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return 0;
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}
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