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![Simon Glass](/assets/img/avatar_default.png)
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
310 lines
6.9 KiB
C
310 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Stefan Roese <sr@denx.de>
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*
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* Derived from the Linux driver version drivers/spi/spi-mt7621.c
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* Copyright (C) 2011 Sergiy <piratfm@gmail.com>
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* Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <log.h>
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#include <spi.h>
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#include <wait_bit.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#define MT7621_RX_FIFO_LEN 32
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#define MT7621_TX_FIFO_LEN 36
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#define MT7621_SPI_TRANS 0x00
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#define MT7621_SPI_TRANS_START BIT(8)
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#define MT7621_SPI_TRANS_BUSY BIT(16)
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#define TRANS_ADDR_SZ GENMASK(20, 19)
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#define TRANS_ADDR_SZ_SHIFT 19
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#define TRANS_MOSI_BCNT GENMASK(3, 0)
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#define TRANS_MOSI_BCNT_SHIFT 0
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#define MT7621_SPI_OPCODE 0x04
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#define MT7621_SPI_DATA0 0x08
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#define MT7621_SPI_DATA4 0x18
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#define MT7621_SPI_MASTER 0x28
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#define MT7621_SPI_MOREBUF 0x2c
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#define MT7621_SPI_POLAR 0x38
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#define MT7621_LSB_FIRST BIT(3)
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#define MT7621_CPOL BIT(4)
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#define MT7621_CPHA BIT(5)
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#define MASTER_MORE_BUFMODE BIT(2)
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#define MASTER_RS_CLK_SEL GENMASK(27, 16)
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#define MASTER_RS_CLK_SEL_SHIFT 16
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#define MASTER_RS_SLAVE_SEL GENMASK(31, 29)
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#define MOREBUF_CMD_CNT GENMASK(29, 24)
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#define MOREBUF_CMD_CNT_SHIFT 24
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#define MOREBUF_MISO_CNT GENMASK(20, 12)
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#define MOREBUF_MISO_CNT_SHIFT 12
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#define MOREBUF_MOSI_CNT GENMASK(8, 0)
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#define MOREBUF_MOSI_CNT_SHIFT 0
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struct mt7621_spi {
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void __iomem *base;
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unsigned int sys_freq;
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};
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static void mt7621_spi_set_cs(struct mt7621_spi *rs, int cs, int enable)
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{
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debug("%s: cs#%d -> %s\n", __func__, cs, enable ? "enable" : "disable");
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if (enable) {
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setbits_le32(rs->base + MT7621_SPI_MASTER,
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MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE);
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iowrite32(BIT(cs), rs->base + MT7621_SPI_POLAR);
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} else {
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iowrite32(0, rs->base + MT7621_SPI_POLAR);
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iowrite32((2 << TRANS_ADDR_SZ_SHIFT) |
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(1 << TRANS_MOSI_BCNT_SHIFT),
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rs->base + MT7621_SPI_TRANS);
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clrbits_le32(rs->base + MT7621_SPI_MASTER,
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MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE);
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}
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}
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static int mt7621_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct mt7621_spi *rs = dev_get_priv(bus);
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u32 reg;
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debug("%s: mode=0x%08x\n", __func__, mode);
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reg = ioread32(rs->base + MT7621_SPI_MASTER);
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reg &= ~MT7621_LSB_FIRST;
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if (mode & SPI_LSB_FIRST)
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reg |= MT7621_LSB_FIRST;
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reg &= ~(MT7621_CPHA | MT7621_CPOL);
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switch (mode & (SPI_CPOL | SPI_CPHA)) {
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case SPI_MODE_0:
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break;
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case SPI_MODE_1:
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reg |= MT7621_CPHA;
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break;
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case SPI_MODE_2:
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reg |= MT7621_CPOL;
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break;
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case SPI_MODE_3:
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reg |= MT7621_CPOL | MT7621_CPHA;
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break;
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}
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iowrite32(reg, rs->base + MT7621_SPI_MASTER);
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return 0;
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}
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static int mt7621_spi_set_speed(struct udevice *bus, uint speed)
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{
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struct mt7621_spi *rs = dev_get_priv(bus);
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u32 rate;
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u32 reg;
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debug("%s: speed=%d\n", __func__, speed);
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rate = DIV_ROUND_UP(rs->sys_freq, speed);
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debug("rate:%u\n", rate);
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if (rate > 4097)
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return -EINVAL;
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if (rate < 2)
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rate = 2;
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reg = ioread32(rs->base + MT7621_SPI_MASTER);
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reg &= ~MASTER_RS_CLK_SEL;
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reg |= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT;
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iowrite32(reg, rs->base + MT7621_SPI_MASTER);
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return 0;
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}
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static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
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{
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int ret;
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ret = wait_for_bit_le32(rs->base + MT7621_SPI_TRANS,
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MT7621_SPI_TRANS_BUSY, 0, 10, 0);
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if (ret)
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pr_err("Timeout in %s!\n", __func__);
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return ret;
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}
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static int mt7621_spi_read(struct mt7621_spi *rs, u8 *buf, size_t len)
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{
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size_t rx_len;
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int i, ret;
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u32 val = 0;
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while (len) {
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rx_len = min_t(size_t, len, MT7621_RX_FIFO_LEN);
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iowrite32((rx_len * 8) << MOREBUF_MISO_CNT_SHIFT,
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rs->base + MT7621_SPI_MOREBUF);
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iowrite32(MT7621_SPI_TRANS_START, rs->base + MT7621_SPI_TRANS);
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ret = mt7621_spi_wait_till_ready(rs);
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if (ret)
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return ret;
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for (i = 0; i < rx_len; i++) {
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if ((i % 4) == 0)
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val = ioread32(rs->base + MT7621_SPI_DATA0 + i);
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*buf++ = val & 0xff;
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val >>= 8;
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}
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len -= rx_len;
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}
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return ret;
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}
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static int mt7621_spi_write(struct mt7621_spi *rs, const u8 *buf, size_t len)
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{
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size_t tx_len, opcode_len, dido_len;
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int i, ret;
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u32 val;
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while (len) {
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tx_len = min_t(size_t, len, MT7621_TX_FIFO_LEN);
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opcode_len = min_t(size_t, tx_len, 4);
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dido_len = tx_len - opcode_len;
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val = 0;
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for (i = 0; i < opcode_len; i++) {
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val <<= 8;
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val |= *buf++;
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}
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iowrite32(val, rs->base + MT7621_SPI_OPCODE);
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val = 0;
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for (i = 0; i < dido_len; i++) {
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val |= (*buf++) << ((i % 4) * 8);
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if ((i % 4 == 3) || (i == dido_len - 1)) {
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iowrite32(val, rs->base + MT7621_SPI_DATA0 +
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(i & ~3));
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val = 0;
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}
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}
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iowrite32(((opcode_len * 8) << MOREBUF_CMD_CNT_SHIFT) |
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((dido_len * 8) << MOREBUF_MOSI_CNT_SHIFT),
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rs->base + MT7621_SPI_MOREBUF);
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iowrite32(MT7621_SPI_TRANS_START, rs->base + MT7621_SPI_TRANS);
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ret = mt7621_spi_wait_till_ready(rs);
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if (ret)
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return ret;
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len -= tx_len;
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}
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return 0;
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}
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static int mt7621_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev->parent;
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struct mt7621_spi *rs = dev_get_priv(bus);
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int total_size = bitlen >> 3;
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int ret = 0;
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debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
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total_size, flags);
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/*
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* This driver only supports half-duplex, so complain and bail out
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* upon full-duplex messages
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*/
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if (dout && din) {
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printf("Only half-duplex SPI transfer supported\n");
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return -EIO;
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}
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mt7621_spi_wait_till_ready(rs);
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/*
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* Set CS active upon start of SPI message. This message can
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* be split upon multiple calls to this xfer function
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*/
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if (flags & SPI_XFER_BEGIN)
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mt7621_spi_set_cs(rs, spi_chip_select(dev), 1);
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if (din)
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ret = mt7621_spi_read(rs, din, total_size);
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else if (dout)
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ret = mt7621_spi_write(rs, dout, total_size);
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if (flags & SPI_XFER_END)
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mt7621_spi_set_cs(rs, spi_chip_select(dev), 0);
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return ret;
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}
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static int mt7621_spi_probe(struct udevice *dev)
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{
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struct mt7621_spi *rs = dev_get_priv(dev);
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struct clk clk;
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int ret;
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rs->base = dev_remap_addr(dev);
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if (!rs->base)
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return -EINVAL;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret < 0) {
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printf("Please provide a clock!\n");
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return ret;
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}
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clk_enable(&clk);
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rs->sys_freq = clk_get_rate(&clk);
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if (!rs->sys_freq) {
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printf("Please provide a valid clock!\n");
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return -EINVAL;
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}
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return 0;
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}
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static const struct dm_spi_ops mt7621_spi_ops = {
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.set_mode = mt7621_spi_set_mode,
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.set_speed = mt7621_spi_set_speed,
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.xfer = mt7621_spi_xfer,
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/*
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* cs_info is not needed, since we require all chip selects to be
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* in the device tree explicitly
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*/
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};
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static const struct udevice_id mt7621_spi_ids[] = {
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{ .compatible = "ralink,mt7621-spi" },
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{ }
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};
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U_BOOT_DRIVER(mt7621_spi) = {
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.name = "mt7621_spi",
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.id = UCLASS_SPI,
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.of_match = mt7621_spi_ids,
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.ops = &mt7621_spi_ops,
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.priv_auto_alloc_size = sizeof(struct mt7621_spi),
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.probe = mt7621_spi_probe,
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};
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