mirror of
https://github.com/brain-hackers/u-boot-brain
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167 lines
3.8 KiB
C
167 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Intel Corporation <www.intel.com>
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*
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*/
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#include <dm.h>
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#include <hang.h>
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#include <wait_bit.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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/* Directory */
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#define DIRUSFER 0x80010
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#define DIRUCASER0 0x80040
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#define DIRUSFMCR 0x80080
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#define DIRUSFMAR 0x80084
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#define DIRUSFMCR_SFID_SHIFT 16
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/* Coherent cache agent interface */
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#define CAIUIDR 0x00ffc
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#define CAIUIDR_CA_GET(v) (((v) & 0x00008000) >> 15)
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#define CAIUIDR_TYPE_GET(v) (((v) & 0x000f0000) >> 16)
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#define CAIUIDR_TYPE_ACE_CAI_DVM_SUPPORT 0
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#define CAIUIDR_TYPE_ACELITE_CAI_DVM_SUPPORT 1
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/* Coherent subsystem */
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#define CSADSER0 0xff040
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#define CSUIDR 0xffff8
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#define CSIDR 0xffffc
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#define CSUIDR_NUMCAIUS_GET(v) (((v) & 0x0000007f) >> 0)
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#define CSUIDR_NUMDIRUS_GET(v) (((v) & 0x003f0000) >> 16)
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#define CSUIDR_NUMCMIUS_GET(v) (((v) & 0x3f000000) >> 24)
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#define CSIDR_NUMSFS_GET(v) (((v) & 0x007c0000) >> 18)
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#define DIR_REG_SZ 0x1000
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#define CAIU_REG_SZ 0x1000
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#define CCU_DIR_REG_ADDR(base, reg, dir) \
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((base) + (reg) + ((dir) * DIR_REG_SZ))
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/* OCRAM firewall register */
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#define OCRAM_FW_01 0x100204
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#define OCRAM_SECURE_REGIONS 4
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#define OCRAM_PRIVILEGED_MASK BIT(29)
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#define OCRAM_SECURE_MASK BIT(30)
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static void ncore_ccu_init_dirs(void __iomem *base)
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{
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ulong i, f;
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int ret;
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u32 num_of_dirs;
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u32 num_of_snoop_filters;
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u32 reg;
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num_of_dirs = CSUIDR_NUMDIRUS_GET(readl(base + CSUIDR));
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num_of_snoop_filters =
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CSIDR_NUMSFS_GET(readl(base + CSIDR)) + 1;
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/* Initialize each snoop filter in each directory */
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for (f = 0; f < num_of_snoop_filters; f++) {
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reg = f << DIRUSFMCR_SFID_SHIFT;
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for (i = 0; i < num_of_dirs; i++) {
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/* Initialize all entries */
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writel(reg, CCU_DIR_REG_ADDR(base, DIRUSFMCR, i));
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/* Poll snoop filter maintenance operation active
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* bit become 0.
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*/
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ret = wait_for_bit_le32((const void *)
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CCU_DIR_REG_ADDR(base,
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DIRUSFMAR, i),
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BIT(0), false, 1000, false);
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if (ret) {
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puts("CCU: Directory initialization failed!\n");
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hang();
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}
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/* Enable snoop filter, a bit per snoop filter */
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setbits_le32((ulong)CCU_DIR_REG_ADDR(base, DIRUSFER, i),
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BIT(f));
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}
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}
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}
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static void ncore_ccu_init_coh_agent(void __iomem *base)
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{
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u32 num_of_coh_agent_intf;
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u32 num_of_dirs;
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u32 reg;
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u32 type;
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u32 i, dir;
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num_of_coh_agent_intf =
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CSUIDR_NUMCAIUS_GET(readl(base + CSUIDR));
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num_of_dirs = CSUIDR_NUMDIRUS_GET(readl(base + CSUIDR));
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for (i = 0; i < num_of_coh_agent_intf; i++) {
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reg = readl(base + CAIUIDR + (i * CAIU_REG_SZ));
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if (CAIUIDR_CA_GET(reg)) {
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/* Caching agent bit is enabled, enable caching agent
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* snoop in each directory
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*/
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for (dir = 0; dir < num_of_dirs; dir++) {
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setbits_le32((ulong)
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CCU_DIR_REG_ADDR(base, DIRUCASER0,
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dir),
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BIT(i));
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}
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}
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type = CAIUIDR_TYPE_GET(reg);
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if (type == CAIUIDR_TYPE_ACE_CAI_DVM_SUPPORT ||
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type == CAIUIDR_TYPE_ACELITE_CAI_DVM_SUPPORT) {
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/* DVM support is enabled, enable ACE DVM snoop*/
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setbits_le32((ulong)(base + CSADSER0),
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BIT(i));
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}
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}
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}
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static void ocram_bypass_firewall(void __iomem *base)
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{
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int i;
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for (i = 0; i < OCRAM_SECURE_REGIONS; i++) {
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clrbits_le32(base + OCRAM_FW_01 + (i * sizeof(u32)),
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OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
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}
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}
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static int ncore_ccu_probe(struct udevice *dev)
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{
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void __iomem *base;
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fdt_addr_t addr;
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addr = dev_read_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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base = (void __iomem *)addr;
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ncore_ccu_init_dirs(base);
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ncore_ccu_init_coh_agent(base);
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ocram_bypass_firewall(base);
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return 0;
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}
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static const struct udevice_id ncore_ccu_ids[] = {
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{ .compatible = "arteris,ncore-ccu" },
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{}
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};
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U_BOOT_DRIVER(ncore_ccu) = {
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.name = "ncore_ccu",
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.id = UCLASS_CACHE,
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.of_match = ncore_ccu_ids,
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.probe = ncore_ccu_probe,
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.flags = DM_FLAG_PRE_RELOC,
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};
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