mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 15:26:03 +09:00
19a387f85d
Enable driver model support for MMC and SATA. Note that DM_MMC requires aliases for your mmc devices so they are added to the dts. Linux does not support enumerating mmc devices by alias so these are not present in the Linux dts. Note that we still need board_mmc_init() and board_mmc_getcd() for not DM SPL to support MMC. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
669 lines
14 KiB
Plaintext
669 lines
14 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 Gateworks Corporation
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/linux-event-codes.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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/* these are used by bootloader for disabling nodes */
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aliases {
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led0 = &led0;
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led1 = &led1;
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led2 = &led2;
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mmc0 = &usdhc3;
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};
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chosen {
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stdout-path = &uart2;
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};
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memory@10000000 {
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device_type = "memory";
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reg = <0x10000000 0x20000000>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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#address-cells = <1>;
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#size-cells = <0>;
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user-pb {
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label = "user_pb";
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gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_0>;
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};
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user-pb1x {
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label = "user_pb1x";
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linux,code = <BTN_1>;
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interrupt-parent = <&gsc>;
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interrupts = <0>;
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};
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key-erased {
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label = "key-erased";
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linux,code = <BTN_2>;
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interrupt-parent = <&gsc>;
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interrupts = <1>;
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};
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eeprom-wp {
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label = "eeprom_wp";
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linux,code = <BTN_3>;
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interrupt-parent = <&gsc>;
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interrupts = <2>;
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};
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tamper {
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label = "tamper";
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linux,code = <BTN_4>;
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interrupt-parent = <&gsc>;
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interrupts = <5>;
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};
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switch-hold {
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label = "switch_hold";
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linux,code = <BTN_5>;
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interrupt-parent = <&gsc>;
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interrupts = <7>;
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};
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_leds>;
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led0: user1 {
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label = "user1";
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gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
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default-state = "on";
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linux,default-trigger = "heartbeat";
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};
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led1: user2 {
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label = "user2";
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gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
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default-state = "off";
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};
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led2: user3 {
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label = "user3";
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gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
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default-state = "off";
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};
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};
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pps {
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compatible = "pps-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pps>;
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gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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reg_5p0v: regulator-5p0v {
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compatible = "regulator-fixed";
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regulator-name = "5P0V";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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};
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reg_wl: regulator-wl {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_wl>;
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compatible = "regulator-fixed";
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regulator-name = "wl";
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gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
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startup-delay-us = <100>;
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enable-active-high;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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&ecspi3 {
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cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi3>;
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status = "okay";
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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phy-mode = "rgmii-id";
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status = "okay";
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand>;
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status = "okay";
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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gsc: gsc@20 {
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compatible = "gw,gsc";
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reg = <0x20>;
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interrupt-parent = <&gpio1>;
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interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#size-cells = <0>;
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adc {
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compatible = "gw,gsc-adc";
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#address-cells = <1>;
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#size-cells = <0>;
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channel@6 {
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gw,mode = <0>;
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reg = <0x06>;
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label = "temp";
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};
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channel@8 {
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gw,mode = <3>;
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reg = <0x08>;
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label = "vdd_bat";
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};
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channel@82 {
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gw,mode = <2>;
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reg = <0x82>;
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label = "vdd_vin";
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gw,voltage-divider-ohms = <22100 1000>;
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gw,voltage-offset-microvolt = <800000>;
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};
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channel@84 {
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gw,mode = <2>;
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reg = <0x84>;
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label = "vdd_5p0";
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gw,voltage-divider-ohms = <22100 10000>;
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};
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channel@86 {
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gw,mode = <2>;
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reg = <0x86>;
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label = "vdd_3p3";
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gw,voltage-divider-ohms = <10000 10000>;
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};
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channel@88 {
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gw,mode = <2>;
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reg = <0x88>;
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label = "vdd_2p5";
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gw,voltage-divider-ohms = <10000 10000>;
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};
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channel@8c {
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gw,mode = <2>;
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reg = <0x8c>;
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label = "vdd_3p0";
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};
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channel@8e {
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gw,mode = <2>;
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reg = <0x8e>;
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label = "vdd_arm";
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};
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channel@90 {
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gw,mode = <2>;
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reg = <0x90>;
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label = "vdd_soc";
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};
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channel@92 {
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gw,mode = <2>;
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reg = <0x92>;
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label = "vdd_1p5";
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};
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channel@98 {
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gw,mode = <2>;
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reg = <0x98>;
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label = "vdd_1p8";
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};
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channel@9a {
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gw,mode = <2>;
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reg = <0x9a>;
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label = "vdd_1p0";
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gw,voltage-divider-ohms = <10000 10000>;
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};
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channel@9c {
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gw,mode = <2>;
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reg = <0x9c>;
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label = "vdd_an1";
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gw,voltage-divider-ohms = <10000 10000>;
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};
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channel@a2 {
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gw,mode = <2>;
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reg = <0xa2>;
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label = "vdd_gsc";
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gw,voltage-divider-ohms = <10000 10000>;
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};
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};
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};
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gsc_gpio: gpio@23 {
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compatible = "nxp,pca9555";
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reg = <0x23>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&gsc>;
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interrupts = <4>;
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};
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eeprom@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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pagesize = <16>;
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};
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eeprom@51 {
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compatible = "atmel,24c02";
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reg = <0x51>;
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pagesize = <16>;
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};
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eeprom@52 {
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compatible = "atmel,24c02";
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reg = <0x52>;
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pagesize = <16>;
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};
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eeprom@53 {
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compatible = "atmel,24c02";
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reg = <0x53>;
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pagesize = <16>;
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};
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rtc@68 {
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compatible = "dallas,ds1672";
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reg = <0x68>;
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};
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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};
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&i2c3 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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accel@19 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_accel>;
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compatible = "st,lis2de12";
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reg = <0x19>;
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st,drdy-int-pin = <1>;
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interrupt-parent = <&gpio7>;
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interrupts = <13 0>;
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interrupt-names = "INT1";
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};
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};
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&pcie {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie>;
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reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&pwm2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
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status = "disabled";
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};
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&pwm3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
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status = "disabled";
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};
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/* off-board RS232 */
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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/* serial console */
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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/* cc1352 */
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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uart-has-rtscts;
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status = "okay";
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};
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/* Sterling-LWB Bluetooth */
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart4>,<&pinctrl_bten>;
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uart-has-rtscts;
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status = "okay";
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bluetooth {
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compatible = "brcm,bcm4330-bt";
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shutdown-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
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};
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};
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/* GPS */
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&uart5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart5>;
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status = "okay";
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};
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&usbotg {
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vbus-supply = <®_5p0v>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg>;
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disable-over-current;
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dr_mode = "host";
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status = "okay";
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};
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&usbh1 {
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status = "okay";
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};
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/* Sterling-LWB SDIO WiFi */
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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vmmc-supply = <®_wl>;
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non-removable;
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bus-width = <4>;
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status = "okay";
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};
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&usdhc3 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
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vmmc-supply = <®_3p3v>;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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};
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&iomuxc {
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pinctrl_accel: accelmuxgrp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
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>;
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};
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pinctrl_bten: btengrp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1
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>;
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};
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pinctrl_ecspi3: escpi3grp {
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fsl,pins = <
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MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
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MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
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MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
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MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
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>;
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};
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pinctrl_enet: enetgrp {
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fsl,pins = <
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MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
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MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
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MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
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MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
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MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
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MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
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MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
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MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
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MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
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MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
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MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
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MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
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MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
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MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
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MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
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MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
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MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
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>;
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};
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pinctrl_gpio_leds: gpioledsgrp {
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fsl,pins = <
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MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
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MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
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MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
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>;
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};
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pinctrl_gpmi_nand: gpminandgrp {
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fsl,pins = <
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MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
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MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
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MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
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MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
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MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
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MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
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MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
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MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
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MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
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MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
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MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
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MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
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MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
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MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
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MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
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MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
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MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2: i2c2grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
|
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c3: i2c3grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
|
|
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_pcie: pciegrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_pps: ppsgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_pwm2: pwm2grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_pwm3: pwm3grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_reg_wl: regwlgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
|
|
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart2: uart2grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
|
|
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart3: uart3grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
|
|
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
|
|
MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1
|
|
MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1
|
|
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x4001b0b1 /* DIO20 */
|
|
MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x4001b0b1 /* DIO14 */
|
|
MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x4001b0b1 /* DIO15 */
|
|
MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 /* TMS */
|
|
MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 /* TCK */
|
|
MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 /* TDO */
|
|
MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 /* TDI */
|
|
MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x4001b0b1 /* RST# */
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart4: uart4grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
|
|
MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
|
|
MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
|
|
MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart5: uart5grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
|
|
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usbotg: usbotggrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
|
|
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
|
|
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
|
|
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
|
|
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
|
|
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3: usdhc3grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
|
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
|
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
|
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
|
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
|
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
|
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
|
|
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
|
|
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
|
|
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
|
|
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
|
|
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
|
|
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
|
|
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
|
|
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
|
|
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
|
|
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
|
|
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
|
|
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
|
|
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
|
|
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
|
|
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
|
|
>;
|
|
};
|
|
|
|
pinctrl_wdog: wdoggrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
|
|
>;
|
|
};
|
|
};
|