mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-09 06:13:21 +09:00
6bacfa6a8e
The environment is the canonical storage location of the mac address, so we're killing off the global data location and moving everything to querying the env directly. The cpus that get converted here: at91rm9200 mpc512x mpc5xxx mpc8260 mpc8xx ppc4xx Signed-off-by: Mike Frysinger <vapier@gentoo.org> CC: Ben Warren <biggerbadderben@gmail.com> CC: John Rigby <jrigby@freescale.com> CC: Stefan Roese <sr@denx.de>
302 lines
7.3 KiB
C
302 lines
7.3 KiB
C
/*
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* (C) Copyright 2003
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* Author : Hamid Ikdoumi (Atmel)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <at91rm9200_net.h>
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#include <net.h>
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#include <miiphy.h>
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/* ----- Ethernet Buffer definitions ----- */
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typedef struct {
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unsigned long addr, size;
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} rbf_t;
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#define RBF_ADDR 0xfffffffc
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#define RBF_OWNER (1<<0)
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#define RBF_WRAP (1<<1)
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#define RBF_BROADCAST (1<<31)
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#define RBF_MULTICAST (1<<30)
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#define RBF_UNICAST (1<<29)
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#define RBF_EXTERNAL (1<<28)
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#define RBF_UNKOWN (1<<27)
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#define RBF_SIZE 0x07ff
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#define RBF_LOCAL4 (1<<26)
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#define RBF_LOCAL3 (1<<25)
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#define RBF_LOCAL2 (1<<24)
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#define RBF_LOCAL1 (1<<23)
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#define RBF_FRAMEMAX 64
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#define RBF_FRAMELEN 0x600
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#ifdef CONFIG_DRIVER_ETHER
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#if defined(CONFIG_CMD_NET)
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/* alignment as per Errata #11 (64 bytes) is insufficient! */
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rbf_t rbfdt[RBF_FRAMEMAX] __attribute((aligned(512)));
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rbf_t *rbfp;
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unsigned char rbf_framebuf[RBF_FRAMEMAX][RBF_FRAMELEN] __attribute((aligned(4)));
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/* structure to interface the PHY */
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AT91S_PhyOps PhyOps;
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AT91PS_EMAC p_mac;
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/*********** EMAC Phy layer Management functions *************************/
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/*
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* Name:
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* at91rm9200_EmacEnableMDIO
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* Description:
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* Enables the MDIO bit in MAC control register
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* Arguments:
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* p_mac - pointer to struct AT91S_EMAC
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* Return value:
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* none
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*/
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void at91rm9200_EmacEnableMDIO (AT91PS_EMAC p_mac)
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{
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/* Mac CTRL reg set for MDIO enable */
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p_mac->EMAC_CTL |= AT91C_EMAC_MPE; /* Management port enable */
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}
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/*
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* Name:
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* at91rm9200_EmacDisableMDIO
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* Description:
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* Disables the MDIO bit in MAC control register
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* Arguments:
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* p_mac - pointer to struct AT91S_EMAC
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* Return value:
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* none
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*/
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void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac)
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{
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/* Mac CTRL reg set for MDIO disable */
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p_mac->EMAC_CTL &= ~AT91C_EMAC_MPE; /* Management port disable */
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}
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/*
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* Name:
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* at91rm9200_EmacReadPhy
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* Description:
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* Reads data from the PHY register
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* Arguments:
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* dev - pointer to struct net_device
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* RegisterAddress - unsigned char
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* pInput - pointer to value read from register
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* Return value:
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* TRUE - if data read successfully
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*/
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UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac,
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unsigned char RegisterAddress,
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unsigned short *pInput)
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{
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p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
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(AT91C_EMAC_RW_R) |
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(RegisterAddress << 18) |
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(AT91C_EMAC_CODE_802_3);
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udelay (10000);
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*pInput = (unsigned short) p_mac->EMAC_MAN;
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return TRUE;
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}
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/*
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* Name:
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* at91rm9200_EmacWritePhy
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* Description:
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* Writes data to the PHY register
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* Arguments:
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* dev - pointer to struct net_device
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* RegisterAddress - unsigned char
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* pOutput - pointer to value to be written in the register
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* Return value:
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* TRUE - if data read successfully
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*/
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UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac,
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unsigned char RegisterAddress,
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unsigned short *pOutput)
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{
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p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
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AT91C_EMAC_CODE_802_3 | AT91C_EMAC_RW_W |
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(RegisterAddress << 18) | *pOutput;
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udelay (10000);
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return TRUE;
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}
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int eth_init (bd_t * bd)
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{
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int ret;
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int i;
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uchar enetaddr[6];
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p_mac = AT91C_BASE_EMAC;
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/* PIO Disable Register */
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*AT91C_PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER |
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AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV |
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AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN |
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AT91C_PA7_ETXCK_EREFCK;
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#ifdef CONFIG_AT91C_USE_RMII
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*AT91C_PIOB_PDR = AT91C_PB19_ERXCK;
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*AT91C_PIOB_BSR = AT91C_PB19_ERXCK;
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#else
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*AT91C_PIOB_PDR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV |
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AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER |
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AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
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/* Select B Register */
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*AT91C_PIOB_BSR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL |
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AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 |
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AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
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#endif
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*AT91C_PMC_PCER = 1 << AT91C_ID_EMAC; /* Peripheral Clock Enable Register */
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p_mac->EMAC_CFG |= AT91C_EMAC_CSR; /* Clear statistics */
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/* Init Ehternet buffers */
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for (i = 0; i < RBF_FRAMEMAX; i++) {
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rbfdt[i].addr = (unsigned long)rbf_framebuf[i];
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rbfdt[i].size = 0;
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}
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rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
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rbfp = &rbfdt[0];
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eth_getenv_enetaddr("ethaddr", enetaddr);
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p_mac->EMAC_SA2L = (enetaddr[3] << 24) | (enetaddr[2] << 16)
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| (enetaddr[1] << 8) | (enetaddr[0]);
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p_mac->EMAC_SA2H = (enetaddr[5] << 8) | (enetaddr[4]);
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p_mac->EMAC_RBQP = (long) (&rbfdt[0]);
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p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
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p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC)
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& ~AT91C_EMAC_CLK;
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#ifdef CONFIG_AT91C_USE_RMII
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p_mac->EMAC_CFG |= AT91C_EMAC_RMII;
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#endif
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#if (AT91C_MASTER_CLOCK > 40000000)
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/* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
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p_mac->EMAC_CFG |= AT91C_EMAC_CLK_HCLK_64;
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#endif
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p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE;
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at91rm9200_GetPhyInterface (& PhyOps);
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if (!PhyOps.IsPhyConnected (p_mac))
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printf ("PHY not connected!!\n\r");
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/* MII management start from here */
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if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) {
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if (!(ret = PhyOps.Init (p_mac))) {
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printf ("MAC: error during MII initialization\n");
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return 0;
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}
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} else {
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printf ("No link\n\r");
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return 0;
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}
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return 0;
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}
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int eth_send (volatile void *packet, int length)
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{
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while (!(p_mac->EMAC_TSR & AT91C_EMAC_BNQ));
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p_mac->EMAC_TAR = (long) packet;
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p_mac->EMAC_TCR = length;
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while (p_mac->EMAC_TCR & 0x7ff);
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p_mac->EMAC_TSR |= AT91C_EMAC_COMP;
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return 0;
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}
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int eth_rx (void)
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{
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int size;
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if (!(rbfp->addr & RBF_OWNER))
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return 0;
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size = rbfp->size & RBF_SIZE;
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NetReceive ((volatile uchar *) (rbfp->addr & RBF_ADDR), size);
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rbfp->addr &= ~RBF_OWNER;
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if (rbfp->addr & RBF_WRAP)
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rbfp = &rbfdt[0];
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else
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rbfp++;
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p_mac->EMAC_RSR |= AT91C_EMAC_REC;
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return size;
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}
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void eth_halt (void)
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{
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};
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
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int at91rm9200_miiphy_read(char *devname, unsigned char addr,
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unsigned char reg, unsigned short * value)
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{
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at91rm9200_EmacEnableMDIO (p_mac);
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at91rm9200_EmacReadPhy (p_mac, reg, value);
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at91rm9200_EmacDisableMDIO (p_mac);
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return 0;
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}
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int at91rm9200_miiphy_write(char *devname, unsigned char addr,
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unsigned char reg, unsigned short value)
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{
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at91rm9200_EmacEnableMDIO (p_mac);
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at91rm9200_EmacWritePhy (p_mac, reg, &value);
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at91rm9200_EmacDisableMDIO (p_mac);
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return 0;
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}
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#endif
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int at91rm9200_miiphy_initialize(bd_t *bis)
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{
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
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miiphy_register("at91rm9200phy", at91rm9200_miiphy_read, at91rm9200_miiphy_write);
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#endif
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return 0;
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}
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#endif
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#endif /* CONFIG_DRIVER_ETHER */
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