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https://github.com/brain-hackers/u-boot-brain
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![Timur Tabi](/assets/img/avatar_default.png)
Most 85xx boards can be built as a 32-bit or a 36-bit. Current code sometimes displays which of these is actually built, but it's inconsistent. This is especially problematic since the "default" build for a given 85xx board can be either one, so if you don't see a message, you can't always know which size is being used. Not only that, but each board includes code that displays the message, so there is duplication. The 'bdinfo' command has been updated to display this information, so we don't need to display it at boot time. The board-specific code is deleted. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
339 lines
8.6 KiB
C
339 lines
8.6 KiB
C
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <linux/compiler.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_portals.h>
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#include <asm/fsl_liodn.h>
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#include <fm_eth.h>
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#include <configs/P3060QDS.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include "../common/qixis.h"
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#include "p3060qds.h"
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#include "p3060qds_qixis.h"
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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u8 sw;
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struct cpu_type *cpu = gd->cpu;
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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unsigned int i;
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printf("Board: %s", cpu->name);
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puts("QDS, ");
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printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
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QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
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sw = QIXIS_READ(brdcfg[0]);
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sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
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if (sw < 0x8)
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printf("vBank: %d\n", sw);
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else if (sw == 0x8)
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puts("Promjet\n");
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else if (sw == 0x9)
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puts("NAND\n");
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else
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printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
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puts("Reset Configuration Word (RCW):");
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for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
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u32 rcw = in_be32(&gur->rcwsr[i]);
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if ((i % 4) == 0)
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printf("\n %08x:", i * 4);
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printf(" %08x", rcw);
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}
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puts("\n");
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puts("SERDES Reference Clocks: ");
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sw = QIXIS_READ(brdcfg[2]);
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for (i = 0; i < 3; i++) {
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static const char * const freq[] = {"100", "125", "Reserved",
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"156.25"};
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unsigned int clock = (sw >> (2 * i)) & 3;
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printf("Bank%u=%sMhz ", i+1, freq[clock]);
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}
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puts("\n");
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return 0;
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}
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int board_early_init_f(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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/* only single DDR controller on QDS board, disable DDR1_MCK4/5 */
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setbits_be32(&gur->ddrclkdr, 0x00030000);
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return 0;
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}
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void board_config_serdes_mux(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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int cfg = (in_be32(&gur->rcwsr[4]) &
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FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
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switch (cfg) {
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case 0x03:
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case 0x06:
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/* set Lane I,J as SGMII */
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QIXIS_WRITE(brdcfg[6], BRDCFG6_SD4MX_B | BRDCFG6_SD3MX_A |
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BRDCFG6_SD2MX_B | BRDCFG6_SD1MX_A);
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break;
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case 0x16:
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case 0x19:
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case 0x1c:
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/* set Lane I,J as Aurora Debug */
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QIXIS_WRITE(brdcfg[6], BRDCFG6_SD4MX_A | BRDCFG6_SD3MX_B |
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BRDCFG6_SD2MX_A | BRDCFG6_SD1MX_B);
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break;
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default:
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puts("Invalid SerDes protocol for P3060QDS\n");
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break;
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}
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}
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void board_config_usb_mux(void)
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{
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u8 brdcfg4, brdcfg5, brdcfg7;
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
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u32 ec1 = rcwsr11 & FSL_CORENET_RCWSR11_EC1;
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u32 ec2 = rcwsr11 & FSL_CORENET_RCWSR11_EC2;
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brdcfg4 = QIXIS_READ(brdcfg[4]);
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brdcfg4 &= ~BRDCFG4_EC_MODE_MASK;
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if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_USB1) &&
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(ec2 == FSL_CORENET_RCWSR11_EC2_USB2)) {
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brdcfg4 |= BRDCFG4_EC2_USB_EC1_USB;
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} else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_USB1) &&
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((ec2 == FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) ||
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(ec2 == FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))) {
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brdcfg4 |= BRDCFG4_EC2_RGMII_EC1_USB;
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} else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1) &&
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(ec2 == FSL_CORENET_RCWSR11_EC2_USB2)) {
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brdcfg4 |= BRDCFG4_EC2_USB_EC1_RGMII;
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} else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1) &&
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((ec2 == FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) ||
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(ec2 == FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))) {
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brdcfg4 |= BRDCFG4_EC2_RGMII_EC1_RGMII;
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} else {
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brdcfg4 |= BRDCFG4_EC2_MII_EC1_MII;
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}
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QIXIS_WRITE(brdcfg[4], brdcfg4);
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brdcfg5 = QIXIS_READ(brdcfg[5]);
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brdcfg5 &= ~(BRDCFG5_USB1ID_MASK | BRDCFG5_USB2ID_MASK);
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brdcfg5 |= (BRDCFG5_USB1ID_CTRL | BRDCFG5_USB2ID_CTRL);
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QIXIS_WRITE(brdcfg[5], brdcfg5);
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brdcfg7 = BRDCFG7_JTAGMX_COP_JTAG | BRDCFG7_IQ1MX_IRQ_EVT |
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BRDCFG7_G1MX_USB1 | BRDCFG7_D1MX_TSEC3USB | BRDCFG7_I3MX_USB1;
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QIXIS_WRITE(brdcfg[7], brdcfg7);
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}
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash + PROMJET region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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/* invalidate existing TLB entry for flash + promjet */
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disable_tlb(flash_esel);
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_256M, 1);
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set_liodns();
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#ifdef CONFIG_SYS_DPAA_QBMAN
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setup_portals();
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#endif
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board_config_serdes_mux();
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board_config_usb_mux();
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return 0;
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}
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static const char *serdes_clock_to_string(u32 clock)
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{
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switch (clock) {
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case SRDS_PLLCR0_RFCK_SEL_100:
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return "100";
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case SRDS_PLLCR0_RFCK_SEL_125:
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return "125";
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case SRDS_PLLCR0_RFCK_SEL_156_25:
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return "156.25";
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default:
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return "150";
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}
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}
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#define NUM_SRDS_BANKS 3
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int misc_init_r(void)
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{
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serdes_corenet_t *srds_regs;
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u32 actual[NUM_SRDS_BANKS];
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unsigned int i;
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u8 sw;
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sw = QIXIS_READ(brdcfg[2]);
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for (i = 0; i < 3; i++) {
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unsigned int clock = (sw >> (2 * i)) & 3;
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switch (clock) {
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case 0:
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actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
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break;
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case 1:
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actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
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break;
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case 3:
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actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
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break;
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default:
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printf("Warning: SDREFCLK%u switch setting of '10' is "
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"unsupported\n", i + 1);
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break;
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}
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}
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srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
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for (i = 0; i < NUM_SRDS_BANKS; i++) {
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u32 pllcr0 = in_be32(&srds_regs->bank[i].pllcr0);
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u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
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if (expected != actual[i]) {
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printf("Warning: SERDES bank %u expects reference clock"
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" %sMHz, but actual is %sMHz\n", i + 1,
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serdes_clock_to_string(expected),
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serdes_clock_to_string(actual[i]));
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}
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}
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return 0;
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}
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/*
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* This is map of CVDD values. 33 means CVDD is 3.3v, 25 means CVDD is 2.5v,
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* 18 means CVDD is 1.8v.
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*/
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static u8 IO_VSEL[] = {
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33, 33, 33, 25, 25, 25, 18, 18, 18,
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33, 33, 33, 25, 25, 25, 18, 18, 18,
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33, 33, 33, 25, 25, 25, 18, 18, 18,
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33, 33, 33, 33, 33
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};
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#define IO_VSEL_MASK 0x1f
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/*
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* different CVDD selects diffenert spi flashs, read dutcfg[3] to get CVDD,
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* then set status of spi flash nodes to 'disabled' according to CVDD.
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* CVDD '33' will select spi flash0 and flash1, CVDD '25' will select spi
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* flash2, CVDD '18' will select spi flash3.
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*/
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void fdt_fixup_board_spi(void *blob)
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{
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u8 sw5 = QIXIS_READ(dutcfg[3]);
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switch (IO_VSEL[sw5 & IO_VSEL_MASK]) {
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/* 3.3v */
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case 33:
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do_fixup_by_compat(blob, "atmel,at45db081d", "status",
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"disabled", strlen("disabled") + 1, 1);
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do_fixup_by_compat(blob, "spansion,sst25wf040", "status",
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"disabled", strlen("disabled") + 1, 1);
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break;
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/* 2.5v */
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case 25:
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do_fixup_by_compat(blob, "spansion,s25sl12801", "status",
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"disabled", strlen("disabled") + 1, 1);
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do_fixup_by_compat(blob, "spansion,en25q32", "status",
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"disabled", strlen("disabled") + 1, 1);
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do_fixup_by_compat(blob, "spansion,sst25wf040", "status",
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"disabled", strlen("disabled") + 1, 1);
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break;
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/* 1.8v */
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case 18:
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do_fixup_by_compat(blob, "spansion,s25sl12801", "status",
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"disabled", strlen("disabled") + 1, 1);
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do_fixup_by_compat(blob, "spansion,en25q32", "status",
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"disabled", strlen("disabled") + 1, 1);
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do_fixup_by_compat(blob, "atmel,at45db081d", "status",
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"disabled", strlen("disabled") + 1, 1);
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break;
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}
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}
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void ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = getenv_bootm_low();
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size = getenv_bootm_size();
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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#ifdef CONFIG_PCI
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pci_of_setup(blob, bd);
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#endif
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fdt_fixup_liodn(blob);
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fdt_fixup_dr_usb(blob, bd);
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fdt_fixup_board_spi(blob);
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#ifdef CONFIG_SYS_DPAA_FMAN
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fdt_fixup_fman_ethernet(blob);
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fdt_fixup_board_enet(blob);
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#endif
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}
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