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https://github.com/brain-hackers/u-boot-brain
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![Timur Tabi](/assets/img/avatar_default.png)
Most 85xx boards can be built as a 32-bit or a 36-bit. Current code sometimes displays which of these is actually built, but it's inconsistent. This is especially problematic since the "default" build for a given 85xx board can be either one, so if you don't see a message, you can't always know which size is being used. Not only that, but each board includes code that displays the message, so there is duplication. The 'bdinfo' command has been updated to display this information, so we don't need to display it at boot time. The board-specific code is deleted. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
267 lines
6.3 KiB
C
267 lines
6.3 KiB
C
/*
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* Copyright 2007-2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_pci.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/io.h>
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#include <asm/fsl_serdes.h>
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#include <miiphy.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <fsl_mdio.h>
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#include <tsec.h>
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#include <asm/fsl_law.h>
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#include <netdev.h>
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#include "../common/ngpixis.h"
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#include "../common/sgmii_riser.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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#ifdef CONFIG_MMC
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ccsr_gur_t *gur = (ccsr_gur_t *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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setbits_be32(&gur->pmuxcr,
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(MPC85xx_PMUXCR_SDHC_CD |
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MPC85xx_PMUXCR_SDHC_WP));
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#endif
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return 0;
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}
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int checkboard(void)
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{
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u8 sw;
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printf("Board: P2020DS Sys ID: 0x%02x, "
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"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
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in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
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sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
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sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
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if (sw < 0x8)
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/* The lower two bits are the actual vbank number */
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printf("vBank: %d\n", sw & 3);
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else
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puts("Promjet\n");
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return 0;
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}
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#if !defined(CONFIG_DDR_SPD)
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/*
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* Fixed sdram init -- doesn't use serial presence detect.
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*/
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phys_size_t fixed_sdram(void)
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{
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volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
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uint d_init;
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ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
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ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
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ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
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ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
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ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
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ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
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ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
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ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
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ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
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ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
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ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
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ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
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ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
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if (!strcmp("performance", getenv("perf_mode"))) {
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/* Performance Mode Values */
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ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
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ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
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ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
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ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
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ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
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asm("sync;isync");
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udelay(500);
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ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
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} else {
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/* Stable Mode Values */
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ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
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ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
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ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
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ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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/* ECC will be assumed in stable mode */
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ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
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ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
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ddr->err_sbe = CONFIG_SYS_DDR_SBE;
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asm("sync;isync");
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udelay(500);
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ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
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}
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#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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d_init = 1;
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debug("DDR - 1st controller: memory initializing\n");
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/*
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* Poll until memory is initialized.
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* 512 Meg at 400 might hit this 200 times or so.
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*/
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while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
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udelay(1000);
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debug("DDR: memory initialized\n\n");
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asm("sync; isync");
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udelay(500);
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#endif
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if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE * 1024 * 1024,
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LAW_TRGT_IF_DDR) < 0) {
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printf("ERROR setting Local Access Windows for DDR\n");
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return 0;
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};
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return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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}
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#endif
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#ifdef CONFIG_PCI
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void pci_init_board(void)
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{
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fsl_pcie_init_board(0);
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}
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#endif
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash + PROMJET region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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/* invalidate existing TLB entry for flash + promjet */
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disable_tlb(flash_esel);
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_256M, 1);
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return 0;
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}
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#ifdef CONFIG_TSEC_ENET
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int board_eth_init(bd_t *bis)
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{
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struct fsl_pq_mdio_info mdio_info;
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struct tsec_info_struct tsec_info[4];
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int num = 0;
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#ifdef CONFIG_TSEC1
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SET_STD_TSEC_INFO(tsec_info[num], 1);
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num++;
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#endif
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#ifdef CONFIG_TSEC2
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SET_STD_TSEC_INFO(tsec_info[num], 2);
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if (is_serdes_configured(SGMII_TSEC2)) {
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puts("eTSEC2 is in sgmii mode.\n");
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tsec_info[num].flags |= TSEC_SGMII;
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}
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num++;
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#endif
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#ifdef CONFIG_TSEC3
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SET_STD_TSEC_INFO(tsec_info[num], 3);
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if (is_serdes_configured(SGMII_TSEC3)) {
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puts("eTSEC3 is in sgmii mode.\n");
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tsec_info[num].flags |= TSEC_SGMII;
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}
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num++;
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#endif
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if (!num) {
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printf("No TSECs initialized\n");
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return 0;
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}
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#ifdef CONFIG_FSL_SGMII_RISER
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fsl_sgmii_riser_init(tsec_info, num);
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#endif
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mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
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mdio_info.name = DEFAULT_MII_NAME;
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fsl_pq_mdio_init(bis, &mdio_info);
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tsec_eth_init(bis, tsec_info, num);
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return pci_eth_init(bis);
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}
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#endif
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = getenv_bootm_low();
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size = getenv_bootm_size();
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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FT_FSL_PCI_SETUP;
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#ifdef CONFIG_FSL_SGMII_RISER
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fsl_sgmii_riser_fdt_fixup(blob);
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#endif
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}
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#endif
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