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![Marek Vasut](/assets/img/avatar_default.png)
diu.c: In function 'diu_set_pixel_clock': diu.c:77: warning: format '%lu' expects type 'long unsigned int', but argument 2 has type 'u32' Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org>
415 lines
11 KiB
C
415 lines
11 KiB
C
/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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* Authors: Timur Tabi <timur@freescale.com>
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*
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* FSL DIU Framebuffer driver
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*/
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#include <common.h>
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#include <command.h>
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#include <linux/ctype.h>
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#include <asm/io.h>
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#include <stdio_dev.h>
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#include <video_fb.h>
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#include "../common/ngpixis.h"
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#include <fsl_diu_fb.h>
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/* The CTL register is called 'csr' in the ngpixis_t structure */
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#define PX_CTL_ALTACC 0x80
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#define PX_BRDCFG0_ELBC_SPI_MASK 0xc0
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#define PX_BRDCFG0_ELBC_SPI_ELBC 0x00
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#define PX_BRDCFG0_ELBC_SPI_NULL 0xc0
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#define PX_BRDCFG0_ELBC_DIU 0x02
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#define PX_BRDCFG1_DVIEN 0x80
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#define PX_BRDCFG1_DFPEN 0x40
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#define PX_BRDCFG1_BACKLIGHT 0x20
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#define PMUXCR_ELBCDIU_MASK 0xc0000000
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#define PMUXCR_ELBCDIU_NOR16 0x80000000
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#define PMUXCR_ELBCDIU_DIU 0x40000000
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/*
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* DIU Area Descriptor
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*
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* Note that we need to byte-swap the value before it's written to the AD
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* register. So even though the registers don't look like they're in the same
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* bit positions as they are on the MPC8610, the same value is written to the
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* AD register on the MPC8610 and on the P1022.
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*/
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#define AD_BYTE_F 0x10000000
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#define AD_ALPHA_C_SHIFT 25
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#define AD_BLUE_C_SHIFT 23
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#define AD_GREEN_C_SHIFT 21
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#define AD_RED_C_SHIFT 19
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#define AD_PIXEL_S_SHIFT 16
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#define AD_COMP_3_SHIFT 12
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#define AD_COMP_2_SHIFT 8
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#define AD_COMP_1_SHIFT 4
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#define AD_COMP_0_SHIFT 0
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/*
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* Variables used by the DIU/LBC switching code. It's safe to makes these
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* global, because the DIU requires DDR, so we'll only run this code after
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* relocation.
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*/
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static u8 px_brdcfg0;
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static u32 pmuxcr;
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static void *lbc_lcs0_ba;
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static void *lbc_lcs1_ba;
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void diu_set_pixel_clock(unsigned int pixclock)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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unsigned long speed_ccb, temp;
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u32 pixval;
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speed_ccb = get_bus_freq(0);
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temp = 1000000000 / pixclock;
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temp *= 1000;
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pixval = speed_ccb / temp;
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debug("DIU pixval = %u\n", pixval);
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/* Modify PXCLK in GUTS CLKDVDR */
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temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
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out_be32(&gur->clkdvdr, temp); /* turn off clock */
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out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));
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}
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int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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const char *name;
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u32 pixel_format;
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u8 temp;
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/* Save the LBC LCS0 and LCS1 addresses for the DIU mux functions */
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lbc_lcs0_ba = (void *)(get_lbc_br(0) & get_lbc_or(0) & 0xFFFF8000);
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lbc_lcs1_ba = (void *)(get_lbc_br(1) & get_lbc_or(1) & 0xFFFF8000);
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pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
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(0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
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(2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
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(8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
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(8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
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temp = in_8(&pixis->brdcfg1);
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if (strncmp(port, "lvds", 4) == 0) {
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/* Single link LVDS */
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temp &= ~PX_BRDCFG1_DVIEN;
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/*
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* LVDS also needs backlight enabled, otherwise the display
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* will be blank.
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*/
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temp |= (PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
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name = "Single-Link LVDS";
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} else { /* DVI */
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/* Enable the DVI port, disable the DFP and the backlight */
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temp &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
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temp |= PX_BRDCFG1_DVIEN;
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name = "DVI";
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}
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printf("DIU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
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out_8(&pixis->brdcfg1, temp);
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/*
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* Enable PIXIS indirect access mode. This is a hack that allows us to
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* access PIXIS registers even when the LBC pins have been muxed to the
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* DIU.
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*/
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setbits_8(&pixis->csr, PX_CTL_ALTACC);
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/*
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* Route the LAD pins to the DIU. This will disable access to the eLBC,
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* which means we won't be able to read/write any NOR flash addresses!
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*/
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out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
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px_brdcfg0 = in_8(lbc_lcs1_ba);
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out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
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/* Set PMUXCR to switch the muxed pins from the LBC to the DIU */
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clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU);
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pmuxcr = in_be32(&gur->pmuxcr);
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return fsl_diu_init(xres, yres, pixel_format, 0);
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}
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/*
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* set_mux_to_lbc - disable the DIU so that we can read/write to elbc
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*
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* On the Freescale P1022, the DIU video signal and the LBC address/data lines
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* share the same pins, which means that when the DIU is active (e.g. the
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* console is on the DVI display), NOR flash cannot be accessed. So we use the
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* weak accessor feature of the CFI flash code to temporarily switch the pin
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* mux from DIU to LBC whenever we want to read or write flash. This has a
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* significant performance penalty, but it's the only way to make it work.
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*
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* There are two muxes: one on the chip, and one on the board. The chip mux
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* controls whether the pins are used for the DIU or the LBC, and it is
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* set via PMUXCR. The board mux controls whether those signals go to
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* the video connector or the NOR flash chips, and it is set via the ngPIXIS.
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*/
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static int set_mux_to_lbc(void)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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/* Switch the muxes only if they're currently set to DIU mode */
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if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
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PMUXCR_ELBCDIU_NOR16) {
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/*
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* In DIU mode, the PIXIS can only be accessed indirectly
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* since we can't read/write the LBC directly.
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*/
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/* Set the board mux to LBC. This will disable the display. */
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out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
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px_brdcfg0 = in_8(lbc_lcs1_ba);
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out_8(lbc_lcs1_ba, (px_brdcfg0 & ~(PX_BRDCFG0_ELBC_SPI_MASK
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| PX_BRDCFG0_ELBC_DIU)) | PX_BRDCFG0_ELBC_SPI_ELBC);
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/* Disable indirect PIXIS mode */
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out_8(lbc_lcs0_ba, offsetof(ngpixis_t, csr));
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clrbits_8(lbc_lcs1_ba, PX_CTL_ALTACC);
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/* Set the chip mux to LBC mode, so that writes go to flash. */
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out_be32(&gur->pmuxcr, (pmuxcr & ~PMUXCR_ELBCDIU_MASK) |
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PMUXCR_ELBCDIU_NOR16);
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in_be32(&gur->pmuxcr);
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return 1;
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}
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return 0;
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}
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/*
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* set_mux_to_diu - re-enable the DIU muxing
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*
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* This function restores the chip and board muxing to point to the DIU.
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*/
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static void set_mux_to_diu(void)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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/* Enable indirect PIXIS mode */
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setbits_8(&pixis->csr, PX_CTL_ALTACC);
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/* Set the board mux to DIU. This will enable the display. */
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out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
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out_8(lbc_lcs1_ba, px_brdcfg0);
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in_8(lbc_lcs1_ba);
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/* Set the chip mux to DIU mode. */
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out_be32(&gur->pmuxcr, pmuxcr);
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in_be32(&gur->pmuxcr);
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}
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/*
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* pixis_read - board-specific function to read from the PIXIS
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*
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* This function overrides the generic pixis_read() function, so that it can
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* use PIXIS indirect mode if necessary.
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*/
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u8 pixis_read(unsigned int reg)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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/* Use indirect mode if the mux is currently set to DIU mode */
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if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
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PMUXCR_ELBCDIU_NOR16) {
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out_8(lbc_lcs0_ba, reg);
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return in_8(lbc_lcs1_ba);
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} else {
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void *p = (void *)PIXIS_BASE;
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return in_8(p + reg);
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}
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}
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/*
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* pixis_write - board-specific function to write to the PIXIS
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*
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* This function overrides the generic pixis_write() function, so that it can
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* use PIXIS indirect mode if necessary.
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*/
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void pixis_write(unsigned int reg, u8 value)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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/* Use indirect mode if the mux is currently set to DIU mode */
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if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
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PMUXCR_ELBCDIU_NOR16) {
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out_8(lbc_lcs0_ba, reg);
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out_8(lbc_lcs1_ba, value);
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/* Do a read-back to ensure the write completed */
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in_8(lbc_lcs1_ba);
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} else {
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void *p = (void *)PIXIS_BASE;
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out_8(p + reg, value);
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}
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}
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void pixis_bank_reset(void)
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{
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/*
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* For some reason, a PIXIS bank reset does not work if the PIXIS is
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* in indirect mode, so switch to direct mode first.
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*/
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set_mux_to_lbc();
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out_8(&pixis->vctl, 0);
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out_8(&pixis->vctl, 1);
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while (1);
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}
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#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
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void flash_write8(u8 value, void *addr)
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{
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int sw = set_mux_to_lbc();
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__raw_writeb(value, addr);
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if (sw) {
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/*
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* To ensure the post-write is completed to eLBC, software must
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* perform a dummy read from one valid address from eLBC space
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* before changing the eLBC_DIU from NOR mode to DIU mode.
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* set_mux_to_diu() includes a sync that will ensure the
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* __raw_readb() completes before it switches the mux.
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*/
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__raw_readb(addr);
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set_mux_to_diu();
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}
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}
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void flash_write16(u16 value, void *addr)
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{
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int sw = set_mux_to_lbc();
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__raw_writew(value, addr);
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if (sw) {
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/*
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* To ensure the post-write is completed to eLBC, software must
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* perform a dummy read from one valid address from eLBC space
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* before changing the eLBC_DIU from NOR mode to DIU mode.
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* set_mux_to_diu() includes a sync that will ensure the
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* __raw_readb() completes before it switches the mux.
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*/
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__raw_readb(addr);
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set_mux_to_diu();
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}
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}
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void flash_write32(u32 value, void *addr)
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{
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int sw = set_mux_to_lbc();
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__raw_writel(value, addr);
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if (sw) {
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/*
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* To ensure the post-write is completed to eLBC, software must
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* perform a dummy read from one valid address from eLBC space
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* before changing the eLBC_DIU from NOR mode to DIU mode.
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* set_mux_to_diu() includes a sync that will ensure the
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* __raw_readb() completes before it switches the mux.
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*/
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__raw_readb(addr);
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set_mux_to_diu();
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}
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}
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void flash_write64(u64 value, void *addr)
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{
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int sw = set_mux_to_lbc();
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uint32_t *p = addr;
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/*
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* There is no __raw_writeq(), so do the write manually. We don't trust
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* the compiler, so we use inline assembly.
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*/
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__asm__ __volatile__(
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"stw%U0%X0 %2,%0;\n"
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"stw%U1%X1 %3,%1;\n"
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: "=m" (*p), "=m" (*(p + 1))
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: "r" ((uint32_t) (value >> 32)), "r" ((uint32_t) (value)));
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if (sw) {
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/*
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* To ensure the post-write is completed to eLBC, software must
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* perform a dummy read from one valid address from eLBC space
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* before changing the eLBC_DIU from NOR mode to DIU mode. We
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* read addr+4 because we just wrote to addr+4, so that's how we
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* maintain execution order. set_mux_to_diu() includes a sync
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* that will ensure the __raw_readb() completes before it
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* switches the mux.
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*/
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__raw_readb(addr + 4);
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set_mux_to_diu();
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}
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}
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u8 flash_read8(void *addr)
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{
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u8 ret;
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int sw = set_mux_to_lbc();
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ret = __raw_readb(addr);
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if (sw)
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set_mux_to_diu();
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return ret;
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}
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u16 flash_read16(void *addr)
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{
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u16 ret;
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int sw = set_mux_to_lbc();
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ret = __raw_readw(addr);
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if (sw)
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set_mux_to_diu();
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return ret;
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}
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u32 flash_read32(void *addr)
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{
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u32 ret;
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int sw = set_mux_to_lbc();
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ret = __raw_readl(addr);
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if (sw)
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set_mux_to_diu();
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return ret;
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}
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u64 flash_read64(void *addr)
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{
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u64 ret;
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int sw = set_mux_to_lbc();
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/* There is no __raw_readq(), so do the read manually */
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ret = *(volatile u64 *)addr;
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if (sw)
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set_mux_to_diu();
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return ret;
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}
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#endif
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