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![Roy Zang](/assets/img/avatar_default.png)
TBI PHY address (TBIPA) register has been set in general frame manager phy init funciton dtsec_init_phy() in drivers/net/fm/eth.c So remove the duplicate code on QorIQ frame manager Ethernet related platforms, which include Hydra board, P4080DS board and P2041rdb board. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Cc: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
528 lines
16 KiB
C
528 lines
16 KiB
C
/*
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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* Author: Timur Tabi <timur@freescale.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* This file handles the board muxing between the Fman Ethernet MACs and
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* the RGMII/SGMII/XGMII PHYs on a Freescale P3041/P5020 "Hydra" reference
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* board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
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* provided by the standard Freescale four-port SGMII riser card. The 10Gb
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* XGMII PHY is provided via the XAUI riser card. Since there is only one
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* Fman device on a P3041 and P5020, we only support one SGMII card and one
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* RGMII card.
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*
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* Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control
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* muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is
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* always the same (0). The value for SGMII depends on which slot the riser is
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* inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII,
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* the value is based on which slot the XAUI is inserted in.
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*
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* The SERDES configuration is used to determine where the SGMII and XAUI cards
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* exist, and also which Fman MACs are routed to which PHYs. So for a given
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* Fman MAC, there is one and only PHY it connects to. MACs cannot be routed
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* to PHYs dynamically.
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*
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*
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* This file also updates the device tree in three ways:
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*
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* 1) The status of each virtual MDIO node that is referenced by an Ethernet
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* node is set to "okay".
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*
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* 2) The phy-handle property of each active Ethernet MAC node is set to the
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* appropriate PHY node.
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*
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* 3) The "mux value" for each virtual MDIO node is set to the correct value,
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* if necessary. Some virtual MDIO nodes do not have configurable mux
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* values, so those values are hard-coded in the DTS. On the HYDRA board,
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* the virtual MDIO node for the SGMII card needs to be updated.
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*
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* For all this to work, the device tree needs to have the following:
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*
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* 1) An alias for each PHY node that an Ethernet node could be routed to.
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*
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* 2) An alias for each real and virtual MDIO node that is disabled by default
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* and might need to be enabled, and also might need to have its mux-value
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* updated.
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/fsl_serdes.h>
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#include <fm_eth.h>
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#include <fsl_mdio.h>
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#include <malloc.h>
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#include <fdt_support.h>
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#include <asm/fsl_dtsec.h>
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#include "../common/ngpixis.h"
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#include "../common/fman.h"
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#ifdef CONFIG_FMAN_ENET
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#define BRDCFG1_EMI1_SEL_MASK 0x70
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#define BRDCFG1_EMI1_SEL_SLOT1 0x10
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#define BRDCFG1_EMI1_SEL_SLOT2 0x20
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#define BRDCFG1_EMI1_SEL_SLOT5 0x30
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#define BRDCFG1_EMI1_SEL_SLOT6 0x40
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#define BRDCFG1_EMI1_SEL_SLOT7 0x50
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#define BRDCFG1_EMI1_SEL_RGMII 0x00
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#define BRDCFG1_EMI1_EN 0x08
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#define BRDCFG1_EMI2_SEL_MASK 0x06
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#define BRDCFG1_EMI2_SEL_SLOT1 0x00
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#define BRDCFG1_EMI2_SEL_SLOT2 0x02
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#define BRDCFG2_REG_GPIO_SEL 0x20
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/*
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* BRDCFG1 mask and value for each MAC
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*
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* This array contains the BRDCFG1 values (in mask/val format) that route the
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* MDIO bus to a particular RGMII or SGMII PHY.
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*/
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struct {
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u8 mask;
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u8 val;
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} mdio_mux[NUM_FM_PORTS];
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/*
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* Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
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* that the mapping must be determined dynamically, or that the lane maps to
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* something other than a board slot
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*/
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static u8 lane_to_slot[] = {
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7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0
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};
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/*
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* Set the board muxing for a given MAC
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*
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* The MDIO layer calls this function every time it wants to talk to a PHY.
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*/
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void hydra_mux_mdio(u8 mask, u8 val)
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{
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clrsetbits_8(&pixis->brdcfg1, mask, val);
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}
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struct hydra_mdio {
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u8 mask;
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u8 val;
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struct mii_dev *realbus;
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};
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static int hydra_mdio_read(struct mii_dev *bus, int addr, int devad,
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int regnum)
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{
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struct hydra_mdio *priv = bus->priv;
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hydra_mux_mdio(priv->mask, priv->val);
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return priv->realbus->read(priv->realbus, addr, devad, regnum);
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}
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static int hydra_mdio_write(struct mii_dev *bus, int addr, int devad,
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int regnum, u16 value)
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{
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struct hydra_mdio *priv = bus->priv;
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hydra_mux_mdio(priv->mask, priv->val);
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return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
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}
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static int hydra_mdio_reset(struct mii_dev *bus)
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{
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struct hydra_mdio *priv = bus->priv;
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return priv->realbus->reset(priv->realbus);
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}
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static void hydra_mdio_set_mux(char *name, u8 mask, u8 val)
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{
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struct mii_dev *bus = miiphy_get_dev_by_name(name);
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struct hydra_mdio *priv = bus->priv;
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priv->mask = mask;
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priv->val = val;
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}
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static int hydra_mdio_init(char *realbusname, char *fakebusname)
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{
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struct hydra_mdio *hmdio;
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struct mii_dev *bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate Hydra MDIO bus\n");
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return -1;
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}
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hmdio = malloc(sizeof(*hmdio));
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if (!hmdio) {
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printf("Failed to allocate Hydra private data\n");
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free(bus);
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return -1;
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}
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bus->read = hydra_mdio_read;
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bus->write = hydra_mdio_write;
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bus->reset = hydra_mdio_reset;
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sprintf(bus->name, fakebusname);
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hmdio->realbus = miiphy_get_dev_by_name(realbusname);
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if (!hmdio->realbus) {
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printf("No bus with name %s\n", realbusname);
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free(bus);
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free(hmdio);
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return -1;
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}
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bus->priv = hmdio;
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return mdio_register(bus);
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}
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/*
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* Given an alias or a path for a node, set the mux value of that node.
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*
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* If 'alias' is not a valid alias, then it is treated as a full path to the
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* node. No error checking is performed.
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*
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* This function is normally called to set the fsl,hydra-mdio-muxval property
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* of a virtual MDIO node.
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*/
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static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux)
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{
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const char *path = fdt_get_alias(fdt, alias);
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if (!path)
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path = alias;
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do_fixup_by_path(fdt, path, "fsl,hydra-mdio-muxval",
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&mux, sizeof(mux), 1);
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}
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/*
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* Given the following ...
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*
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* 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
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* compatible string and 'addr' physical address)
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*
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* 2) An Fman port
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*
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* ... update the phy-handle property of the Ethernet node to point to the
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* right PHY. This assumes that we already know the PHY for each port. That
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* information is stored in mdio_mux[].
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*
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* The offset of the Fman Ethernet node is also passed in for convenience, but
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* it is not used, and we recalculate the offset anyway.
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*
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* Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
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* Inside the Fman, "ports" are things that connect to MACs. We only call them
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* ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
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* and ports are the same thing.
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*
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* Note that this code would be cleaner if had a function called
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* fm_info_get_phy_address(), which returns a value from the fm1_dtsec_info[]
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* array. That's because all we're doing is figuring out the PHY address for
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* a given Fman MAC and writing it to the device tree. Well, we already did
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* the hard work to figure that out in board_eth_init(), so it's silly to
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* repeat that here.
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*/
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void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
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enum fm_port port, int offset)
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{
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unsigned int mux = mdio_mux[port].val & mdio_mux[port].mask;
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char phy[16];
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if (port == FM1_10GEC1) {
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/* XAUI */
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int lane = serdes_get_first_lane(XAUI_FM1);
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if (lane >= 0) {
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/* The XAUI PHY is identified by the slot */
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sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
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fdt_set_phy_handle(fdt, compat, addr, phy);
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}
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return;
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}
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if (mux == BRDCFG1_EMI1_SEL_RGMII) {
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/* RGMII */
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/* The RGMII PHY is identified by the MAC connected to it */
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sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1);
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fdt_set_phy_handle(fdt, compat, addr, phy);
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}
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/* If it's not RGMII or XGMII, it must be SGMII */
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if (mux) {
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/* The SGMII PHY is identified by the MAC connected to it */
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sprintf(phy, "phy_sgmii_%x",
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CONFIG_SYS_FM1_DTSEC1_PHY_ADDR + (port - FM1_DTSEC1));
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fdt_set_phy_handle(fdt, compat, addr, phy);
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}
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}
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#define PIXIS_SW2_LANE_23_SEL 0x80
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#define PIXIS_SW2_LANE_45_SEL 0x40
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#define PIXIS_SW2_LANE_67_SEL_MASK 0x30
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#define PIXIS_SW2_LANE_67_SEL_5 0x00
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#define PIXIS_SW2_LANE_67_SEL_6 0x20
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#define PIXIS_SW2_LANE_67_SEL_7 0x10
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#define PIXIS_SW2_LANE_8_SEL 0x08
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#define PIXIS_SW2_LANE_1617_SEL 0x04
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/*
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* Initialize the lane_to_slot[] array.
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*
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* On the P4080DS "Expedition" board, the mapping of SERDES lanes to board
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* slots is hard-coded. On the Hydra board, however, the mapping is controlled
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* by board switch SW2, so the lane_to_slot[] array needs to be dynamically
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* initialized.
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*/
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static void initialize_lane_to_slot(void)
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{
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u8 sw2 = in_8(&PIXIS_SW(2));
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lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4;
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lane_to_slot[3] = lane_to_slot[2];
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lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6;
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lane_to_slot[5] = lane_to_slot[4];
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switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) {
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case PIXIS_SW2_LANE_67_SEL_5:
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lane_to_slot[6] = 5;
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break;
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case PIXIS_SW2_LANE_67_SEL_6:
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lane_to_slot[6] = 6;
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break;
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case PIXIS_SW2_LANE_67_SEL_7:
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lane_to_slot[6] = 7;
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break;
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}
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lane_to_slot[7] = lane_to_slot[6];
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lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0;
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lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0;
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lane_to_slot[17] = lane_to_slot[16];
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}
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#endif /* #ifdef CONFIG_FMAN_ENET */
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/*
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* Configure the status for the virtual MDIO nodes
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*
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* Rather than create the virtual MDIO nodes from scratch for each active
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* virtual MDIO, we expect the DTS to have the nodes defined already, and we
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* only enable the ones that are actually active.
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*
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* We assume that the DTS already hard-codes the status for all the
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* virtual MDIO nodes to "disabled", so all we need to do is enable the
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* active ones.
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*
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* For SGMII, we also need to set the mux value in the node.
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*/
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void fdt_fixup_board_enet(void *fdt)
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{
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#ifdef CONFIG_FMAN_ENET
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unsigned int i;
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int lane;
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for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
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int idx = i - FM1_DTSEC1;
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switch (fm_info_get_enet_if(i)) {
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case PHY_INTERFACE_MODE_SGMII:
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lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
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if (lane >= 0) {
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fdt_status_okay_by_alias(fdt, "emi1_sgmii");
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/* Also set the MUX value */
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fdt_set_mdio_mux(fdt, "emi1_sgmii",
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mdio_mux[i].val);
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}
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break;
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case PHY_INTERFACE_MODE_RGMII:
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fdt_status_okay_by_alias(fdt, "emi1_rgmii");
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break;
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default:
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break;
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}
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}
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lane = serdes_get_first_lane(XAUI_FM1);
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if (lane >= 0)
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fdt_status_okay_by_alias(fdt, "emi2_xgmii");
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#endif
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}
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_FMAN_ENET
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struct fsl_pq_mdio_info dtsec_mdio_info;
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struct tgec_mdio_info tgec_mdio_info;
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unsigned int i, slot;
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int lane;
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printf("Initializing Fman\n");
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initialize_lane_to_slot();
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/* We want to use the PIXIS to configure MUX routing, not GPIOs. */
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setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);
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memset(mdio_mux, 0, sizeof(mdio_mux));
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dtsec_mdio_info.regs =
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(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
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dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
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/* Register the real 1G MDIO bus */
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fsl_pq_mdio_init(bis, &dtsec_mdio_info);
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tgec_mdio_info.regs =
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(struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
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tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
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/* Register the real 10G MDIO bus */
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fm_tgec_mdio_init(bis, &tgec_mdio_info);
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/* Register the three virtual MDIO front-ends */
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hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_RGMII_MDIO");
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hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_SGMII_MDIO");
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/*
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* Program the DTSEC PHY addresses assuming that they are all SGMII.
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* For any DTSEC that's RGMII, we'll override its PHY address later.
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* We assume that DTSEC5 is only used for RGMII.
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*/
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fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
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for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
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int idx = i - FM1_DTSEC1;
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switch (fm_info_get_enet_if(i)) {
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case PHY_INTERFACE_MODE_SGMII:
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lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
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if (lane < 0)
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break;
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slot = lane_to_slot[lane];
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mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
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switch (slot) {
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case 1:
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/* Always DTSEC5 on Bank 3 */
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mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
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BRDCFG1_EMI1_EN;
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break;
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case 2:
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mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
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BRDCFG1_EMI1_EN;
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break;
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case 5:
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mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
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BRDCFG1_EMI1_EN;
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|
break;
|
|
case 6:
|
|
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
|
|
BRDCFG1_EMI1_EN;
|
|
break;
|
|
case 7:
|
|
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
|
|
BRDCFG1_EMI1_EN;
|
|
break;
|
|
};
|
|
|
|
hydra_mdio_set_mux("HYDRA_SGMII_MDIO",
|
|
mdio_mux[i].mask, mdio_mux[i].val);
|
|
fm_info_set_mdio(i,
|
|
miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"));
|
|
break;
|
|
case PHY_INTERFACE_MODE_RGMII:
|
|
/*
|
|
* If DTSEC4 is RGMII, then it's routed via via EC1 to
|
|
* the first on-board RGMII port. If DTSEC5 is RGMII,
|
|
* then it's routed via via EC2 to the second on-board
|
|
* RGMII port. The other DTSECs cannot be routed to
|
|
* RGMII.
|
|
*/
|
|
fm_info_set_phy_address(i, i == FM1_DTSEC4 ? 0 : 1);
|
|
mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
|
|
mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
|
|
BRDCFG1_EMI1_EN;
|
|
hydra_mdio_set_mux("HYDRA_RGMII_MDIO",
|
|
mdio_mux[i].mask, mdio_mux[i].val);
|
|
fm_info_set_mdio(i,
|
|
miiphy_get_dev_by_name("HYDRA_RGMII_MDIO"));
|
|
break;
|
|
case PHY_INTERFACE_MODE_NONE:
|
|
fm_info_set_phy_address(i, 0);
|
|
break;
|
|
default:
|
|
printf("Fman1: DTSEC%u set to unknown interface %i\n",
|
|
idx + 1, fm_info_get_enet_if(i));
|
|
fm_info_set_phy_address(i, 0);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* For 10G, we only support one XAUI card per Fman. If present, then we
|
|
* force its routing and never touch those bits again, which removes the
|
|
* need for Linux to do any muxing. This works because of the way
|
|
* BRDCFG1 is defined, but it's a bit hackish.
|
|
*
|
|
* The PHY address for the XAUI card depends on which slot it's in. The
|
|
* macros we use imply that the PHY address is based on which FM, but
|
|
* that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
|
|
* and FM2 could only use a XAUI in slot 4. On the Hydra board, we
|
|
* check the actual slot and just use the macros as-is, even though
|
|
* the P3041 and P5020 only have one Fman.
|
|
*/
|
|
lane = serdes_get_first_lane(XAUI_FM1);
|
|
if (lane >= 0) {
|
|
slot = lane_to_slot[lane];
|
|
if (slot == 1) {
|
|
/* XAUI card is in slot 1 */
|
|
clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK,
|
|
BRDCFG1_EMI2_SEL_SLOT1);
|
|
fm_info_set_phy_address(FM1_10GEC1,
|
|
CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
|
|
} else {
|
|
/* XAUI card is in slot 2 */
|
|
clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK,
|
|
BRDCFG1_EMI2_SEL_SLOT2);
|
|
fm_info_set_phy_address(FM1_10GEC1,
|
|
CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
|
|
}
|
|
}
|
|
|
|
fm_info_set_mdio(FM1_10GEC1,
|
|
miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
|
|
|
|
cpu_eth_init(bis);
|
|
#endif
|
|
|
|
return pci_eth_init(bis);
|
|
}
|