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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 08:28:51 +09:00
![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
583 lines
13 KiB
C
583 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Faraday FTGMAC100 Ethernet
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*
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* (C) Copyright 2009 Faraday Technology
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* Po-Yu Chuang <ratbert@faraday-tech.com>
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*
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* (C) Copyright 2010 Andes Technology
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* Macpaul Lin <macpaul@andestech.com>
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*/
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#include <config.h>
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#include <common.h>
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#include <malloc.h>
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#include <net.h>
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#include <asm/io.h>
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#include <asm/dma-mapping.h>
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#include <linux/mii.h>
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#include "ftgmac100.h"
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#define ETH_ZLEN 60
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#define CFG_XBUF_SIZE 1536
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/* RBSR - hw default init value is also 0x640 */
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#define RBSR_DEFAULT_VALUE 0x640
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/* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
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#define PKTBUFSTX 4 /* must be power of 2 */
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struct ftgmac100_data {
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ulong txdes_dma;
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struct ftgmac100_txdes *txdes;
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ulong rxdes_dma;
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struct ftgmac100_rxdes *rxdes;
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int tx_index;
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int rx_index;
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int phy_addr;
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};
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/*
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* struct mii_bus functions
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*/
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static int ftgmac100_mdiobus_read(struct eth_device *dev, int phy_addr,
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int regnum)
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{
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struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
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int phycr;
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int i;
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phycr = readl(&ftgmac100->phycr);
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/* preserve MDC cycle threshold */
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phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
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phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr)
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| FTGMAC100_PHYCR_REGAD(regnum)
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| FTGMAC100_PHYCR_MIIRD;
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writel(phycr, &ftgmac100->phycr);
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for (i = 0; i < 10; i++) {
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phycr = readl(&ftgmac100->phycr);
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if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
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int data;
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data = readl(&ftgmac100->phydata);
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return FTGMAC100_PHYDATA_MIIRDATA(data);
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}
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mdelay(10);
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}
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debug("mdio read timed out\n");
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return -1;
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}
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static int ftgmac100_mdiobus_write(struct eth_device *dev, int phy_addr,
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int regnum, u16 value)
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{
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struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
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int phycr;
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int data;
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int i;
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phycr = readl(&ftgmac100->phycr);
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/* preserve MDC cycle threshold */
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phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
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phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr)
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| FTGMAC100_PHYCR_REGAD(regnum)
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| FTGMAC100_PHYCR_MIIWR;
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data = FTGMAC100_PHYDATA_MIIWDATA(value);
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writel(data, &ftgmac100->phydata);
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writel(phycr, &ftgmac100->phycr);
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for (i = 0; i < 10; i++) {
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phycr = readl(&ftgmac100->phycr);
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if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) {
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debug("(phycr & FTGMAC100_PHYCR_MIIWR) == 0: " \
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"phy_addr: %x\n", phy_addr);
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return 0;
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}
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mdelay(1);
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}
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debug("mdio write timed out\n");
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return -1;
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}
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int ftgmac100_phy_read(struct eth_device *dev, int addr, int reg, u16 *value)
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{
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*value = ftgmac100_mdiobus_read(dev , addr, reg);
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if (*value == -1)
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return -1;
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return 0;
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}
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int ftgmac100_phy_write(struct eth_device *dev, int addr, int reg, u16 value)
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{
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if (ftgmac100_mdiobus_write(dev, addr, reg, value) == -1)
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return -1;
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return 0;
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}
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static int ftgmac100_phy_reset(struct eth_device *dev)
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{
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struct ftgmac100_data *priv = dev->priv;
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int i;
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u16 status, adv;
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adv = ADVERTISE_CSMA | ADVERTISE_ALL;
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ftgmac100_phy_write(dev, priv->phy_addr, MII_ADVERTISE, adv);
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printf("%s: Starting autonegotiation...\n", dev->name);
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ftgmac100_phy_write(dev, priv->phy_addr,
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MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART));
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for (i = 0; i < 100000 / 100; i++) {
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ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status);
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if (status & BMSR_ANEGCOMPLETE)
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break;
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mdelay(1);
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}
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if (status & BMSR_ANEGCOMPLETE) {
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printf("%s: Autonegotiation complete\n", dev->name);
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} else {
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printf("%s: Autonegotiation timed out (status=0x%04x)\n",
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dev->name, status);
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return 0;
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}
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return 1;
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}
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static int ftgmac100_phy_init(struct eth_device *dev)
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{
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struct ftgmac100_data *priv = dev->priv;
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int phy_addr;
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u16 phy_id, status, adv, lpa, stat_ge;
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int media, speed, duplex;
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int i;
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/* Check if the PHY is up to snuff... */
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for (phy_addr = 0; phy_addr < CONFIG_PHY_MAX_ADDR; phy_addr++) {
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ftgmac100_phy_read(dev, phy_addr, MII_PHYSID1, &phy_id);
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/*
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* When it is unable to found PHY,
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* the interface usually return 0xffff or 0x0000
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*/
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if (phy_id != 0xffff && phy_id != 0x0) {
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printf("%s: found PHY at 0x%02x\n",
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dev->name, phy_addr);
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priv->phy_addr = phy_addr;
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break;
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}
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}
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if (phy_id == 0xffff || phy_id == 0x0) {
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printf("%s: no PHY present\n", dev->name);
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return 0;
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}
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ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status);
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if (!(status & BMSR_LSTATUS)) {
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/* Try to re-negotiate if we don't have link already. */
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ftgmac100_phy_reset(dev);
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for (i = 0; i < 100000 / 100; i++) {
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ftgmac100_phy_read(dev, priv->phy_addr,
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MII_BMSR, &status);
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if (status & BMSR_LSTATUS)
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break;
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udelay(100);
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}
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}
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if (!(status & BMSR_LSTATUS)) {
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printf("%s: link down\n", dev->name);
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return 0;
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}
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#ifdef CONFIG_FTGMAC100_EGIGA
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/* 1000 Base-T Status Register */
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ftgmac100_phy_read(dev, priv->phy_addr,
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MII_STAT1000, &stat_ge);
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speed = (stat_ge & (LPA_1000FULL | LPA_1000HALF)
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? 1 : 0);
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duplex = ((stat_ge & LPA_1000FULL)
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? 1 : 0);
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if (speed) { /* Speed is 1000 */
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printf("%s: link up, 1000bps %s-duplex\n",
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dev->name, duplex ? "full" : "half");
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return 0;
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}
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#endif
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ftgmac100_phy_read(dev, priv->phy_addr, MII_ADVERTISE, &adv);
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ftgmac100_phy_read(dev, priv->phy_addr, MII_LPA, &lpa);
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media = mii_nway_result(lpa & adv);
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speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? 1 : 0);
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duplex = (media & ADVERTISE_FULL) ? 1 : 0;
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printf("%s: link up, %sMbps %s-duplex\n",
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dev->name, speed ? "100" : "10", duplex ? "full" : "half");
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return 1;
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}
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static int ftgmac100_update_link_speed(struct eth_device *dev)
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{
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struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
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struct ftgmac100_data *priv = dev->priv;
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unsigned short stat_fe;
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unsigned short stat_ge;
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unsigned int maccr;
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#ifdef CONFIG_FTGMAC100_EGIGA
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/* 1000 Base-T Status Register */
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ftgmac100_phy_read(dev, priv->phy_addr, MII_STAT1000, &stat_ge);
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#endif
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ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &stat_fe);
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if (!(stat_fe & BMSR_LSTATUS)) /* link status up? */
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return 0;
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/* read MAC control register and clear related bits */
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maccr = readl(&ftgmac100->maccr) &
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~(FTGMAC100_MACCR_GIGA_MODE |
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FTGMAC100_MACCR_FAST_MODE |
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FTGMAC100_MACCR_FULLDUP);
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#ifdef CONFIG_FTGMAC100_EGIGA
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if (stat_ge & LPA_1000FULL) {
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/* set gmac for 1000BaseTX and Full Duplex */
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maccr |= FTGMAC100_MACCR_GIGA_MODE | FTGMAC100_MACCR_FULLDUP;
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}
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if (stat_ge & LPA_1000HALF) {
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/* set gmac for 1000BaseTX and Half Duplex */
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maccr |= FTGMAC100_MACCR_GIGA_MODE;
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}
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#endif
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if (stat_fe & BMSR_100FULL) {
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/* set MII for 100BaseTX and Full Duplex */
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maccr |= FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_FULLDUP;
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}
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if (stat_fe & BMSR_10FULL) {
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/* set MII for 10BaseT and Full Duplex */
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maccr |= FTGMAC100_MACCR_FULLDUP;
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}
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if (stat_fe & BMSR_100HALF) {
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/* set MII for 100BaseTX and Half Duplex */
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maccr |= FTGMAC100_MACCR_FAST_MODE;
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}
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if (stat_fe & BMSR_10HALF) {
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/* set MII for 10BaseT and Half Duplex */
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/* we have already clear these bits, do nothing */
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;
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}
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/* update MII config into maccr */
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writel(maccr, &ftgmac100->maccr);
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return 1;
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}
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/*
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* Reset MAC
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*/
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static void ftgmac100_reset(struct eth_device *dev)
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{
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struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
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debug("%s()\n", __func__);
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writel(FTGMAC100_MACCR_SW_RST, &ftgmac100->maccr);
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while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST)
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;
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}
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/*
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* Set MAC address
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*/
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static void ftgmac100_set_mac(struct eth_device *dev,
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const unsigned char *mac)
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{
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struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
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unsigned int maddr = mac[0] << 8 | mac[1];
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unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
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debug("%s(%x %x)\n", __func__, maddr, laddr);
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writel(maddr, &ftgmac100->mac_madr);
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writel(laddr, &ftgmac100->mac_ladr);
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}
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static void ftgmac100_set_mac_from_env(struct eth_device *dev)
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{
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eth_env_get_enetaddr("ethaddr", dev->enetaddr);
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ftgmac100_set_mac(dev, dev->enetaddr);
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}
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/*
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* disable transmitter, receiver
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*/
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static void ftgmac100_halt(struct eth_device *dev)
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{
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struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
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debug("%s()\n", __func__);
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writel(0, &ftgmac100->maccr);
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}
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static int ftgmac100_init(struct eth_device *dev, bd_t *bd)
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{
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struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
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struct ftgmac100_data *priv = dev->priv;
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struct ftgmac100_txdes *txdes;
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struct ftgmac100_rxdes *rxdes;
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unsigned int maccr;
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void *buf;
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int i;
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debug("%s()\n", __func__);
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if (!priv->txdes) {
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txdes = dma_alloc_coherent(
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sizeof(*txdes) * PKTBUFSTX, &priv->txdes_dma);
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if (!txdes)
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panic("ftgmac100: out of memory\n");
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memset(txdes, 0, sizeof(*txdes) * PKTBUFSTX);
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priv->txdes = txdes;
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}
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txdes = priv->txdes;
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if (!priv->rxdes) {
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rxdes = dma_alloc_coherent(
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sizeof(*rxdes) * PKTBUFSRX, &priv->rxdes_dma);
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if (!rxdes)
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panic("ftgmac100: out of memory\n");
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memset(rxdes, 0, sizeof(*rxdes) * PKTBUFSRX);
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priv->rxdes = rxdes;
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}
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rxdes = priv->rxdes;
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/* set the ethernet address */
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ftgmac100_set_mac_from_env(dev);
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/* disable all interrupts */
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writel(0, &ftgmac100->ier);
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/* initialize descriptors */
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priv->tx_index = 0;
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priv->rx_index = 0;
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txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
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rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
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for (i = 0; i < PKTBUFSTX; i++) {
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/* TXBUF_BADR */
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if (!txdes[i].txdes2) {
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buf = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);
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if (!buf)
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panic("ftgmac100: out of memory\n");
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txdes[i].txdes3 = virt_to_phys(buf);
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txdes[i].txdes2 = (uint)buf;
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}
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txdes[i].txdes1 = 0;
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}
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for (i = 0; i < PKTBUFSRX; i++) {
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/* RXBUF_BADR */
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if (!rxdes[i].rxdes2) {
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buf = net_rx_packets[i];
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rxdes[i].rxdes3 = virt_to_phys(buf);
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rxdes[i].rxdes2 = (uint)buf;
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}
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rxdes[i].rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
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}
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/* transmit ring */
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writel(priv->txdes_dma, &ftgmac100->txr_badr);
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/* receive ring */
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writel(priv->rxdes_dma, &ftgmac100->rxr_badr);
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/* poll receive descriptor automatically */
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writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
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/* config receive buffer size register */
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writel(FTGMAC100_RBSR_SIZE(RBSR_DEFAULT_VALUE), &ftgmac100->rbsr);
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/* enable transmitter, receiver */
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maccr = FTGMAC100_MACCR_TXMAC_EN |
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FTGMAC100_MACCR_RXMAC_EN |
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FTGMAC100_MACCR_TXDMA_EN |
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FTGMAC100_MACCR_RXDMA_EN |
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FTGMAC100_MACCR_CRC_APD |
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FTGMAC100_MACCR_FULLDUP |
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FTGMAC100_MACCR_RX_RUNT |
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FTGMAC100_MACCR_RX_BROADPKT;
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writel(maccr, &ftgmac100->maccr);
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if (!ftgmac100_phy_init(dev)) {
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if (!ftgmac100_update_link_speed(dev))
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return -1;
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}
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return 0;
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}
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/*
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* Get a data block via Ethernet
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*/
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static int ftgmac100_recv(struct eth_device *dev)
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{
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struct ftgmac100_data *priv = dev->priv;
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struct ftgmac100_rxdes *curr_des;
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unsigned short rxlen;
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curr_des = &priv->rxdes[priv->rx_index];
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if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY))
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return -1;
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if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR |
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FTGMAC100_RXDES0_CRC_ERR |
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FTGMAC100_RXDES0_FTL |
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FTGMAC100_RXDES0_RUNT |
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FTGMAC100_RXDES0_RX_ODD_NB)) {
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return -1;
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}
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rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0);
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debug("%s(): RX buffer %d, %x received\n",
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__func__, priv->rx_index, rxlen);
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/* invalidate d-cache */
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dma_map_single((void *)curr_des->rxdes2, rxlen, DMA_FROM_DEVICE);
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|
|
/* pass the packet up to the protocol layers. */
|
|
net_process_received_packet((void *)curr_des->rxdes2, rxlen);
|
|
|
|
/* release buffer to DMA */
|
|
curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
|
|
|
|
priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Send a data block via Ethernet
|
|
*/
|
|
static int ftgmac100_send(struct eth_device *dev, void *packet, int length)
|
|
{
|
|
struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
|
|
struct ftgmac100_data *priv = dev->priv;
|
|
struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index];
|
|
|
|
if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) {
|
|
debug("%s(): no TX descriptor available\n", __func__);
|
|
return -1;
|
|
}
|
|
|
|
debug("%s(%x, %x)\n", __func__, (int)packet, length);
|
|
|
|
length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
|
|
|
|
memcpy((void *)curr_des->txdes2, (void *)packet, length);
|
|
dma_map_single((void *)curr_des->txdes2, length, DMA_TO_DEVICE);
|
|
|
|
/* only one descriptor on TXBUF */
|
|
curr_des->txdes0 &= FTGMAC100_TXDES0_EDOTR;
|
|
curr_des->txdes0 |= FTGMAC100_TXDES0_FTS |
|
|
FTGMAC100_TXDES0_LTS |
|
|
FTGMAC100_TXDES0_TXBUF_SIZE(length) |
|
|
FTGMAC100_TXDES0_TXDMA_OWN ;
|
|
|
|
/* start transmit */
|
|
writel(1, &ftgmac100->txpd);
|
|
|
|
debug("%s(): packet sent\n", __func__);
|
|
|
|
priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int ftgmac100_initialize(bd_t *bd)
|
|
{
|
|
struct eth_device *dev;
|
|
struct ftgmac100_data *priv;
|
|
|
|
dev = malloc(sizeof *dev);
|
|
if (!dev) {
|
|
printf("%s(): failed to allocate dev\n", __func__);
|
|
goto out;
|
|
}
|
|
|
|
/* Transmit and receive descriptors should align to 16 bytes */
|
|
priv = memalign(16, sizeof(struct ftgmac100_data));
|
|
if (!priv) {
|
|
printf("%s(): failed to allocate priv\n", __func__);
|
|
goto free_dev;
|
|
}
|
|
|
|
memset(dev, 0, sizeof(*dev));
|
|
memset(priv, 0, sizeof(*priv));
|
|
|
|
strcpy(dev->name, "FTGMAC100");
|
|
dev->iobase = CONFIG_FTGMAC100_BASE;
|
|
dev->init = ftgmac100_init;
|
|
dev->halt = ftgmac100_halt;
|
|
dev->send = ftgmac100_send;
|
|
dev->recv = ftgmac100_recv;
|
|
dev->priv = priv;
|
|
|
|
eth_register(dev);
|
|
|
|
ftgmac100_reset(dev);
|
|
|
|
return 1;
|
|
|
|
free_dev:
|
|
free(dev);
|
|
out:
|
|
return 0;
|
|
}
|