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u-boot-brain/board/ti/beagle_x15
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Lokesh Vutla 802bb57a58 ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value 
The value in SDRAM_REF_CTRL controls the delay time between
the initial rising edge of DDR_RESETn to rising edge of DDR_CKE
(JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL
should be written with a value corresponding to 500us delay before
starting DDR initialization sequence, and configure proper
value at the end of sequence.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-02-16 12:41:40 -05:00
..
board.c ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value 2015-02-16 12:41:40 -05:00
Kconfig beagle_x15: add board support for Beagle x15 2014-12-04 11:04:39 -05:00
MAINTAINERS omap: beagle_x15: add MAINTAINERS 2015-01-12 09:38:47 -05:00
Makefile beagle_x15: add board support for Beagle x15 2014-12-04 11:04:39 -05:00
mux_data.h beagle_x15: add board support for Beagle x15 2014-12-04 11:04:39 -05:00