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![Stefan Roese](/assets/img/avatar_default.png)
This patch adds DM based support for the Armada 3700 EHCI controller. The address windows don't need to get configured in this case. The difference here is detected via DT compatible property at runtime. With this support and the DM xHCI driver, both XHCI and eHCI can be used simultaniously on the MVEBU boards now. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com> Acked-by: Marek Vasut <marex@denx.de>
233 lines
5.8 KiB
C
233 lines
5.8 KiB
C
/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <usb.h>
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#include "ehci.h"
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#include <linux/mbus.h>
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#include <asm/arch/cpu.h>
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#include <dm.h>
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#if defined(CONFIG_KIRKWOOD)
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#include <asm/arch/soc.h>
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#elif defined(CONFIG_ORION5X)
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#include <asm/arch/orion5x.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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#define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4))
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#define USB_WINDOW_BASE(i) (0x324 + ((i) << 4))
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#define USB_TARGET_DRAM 0x0
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#define USB2_SBUSCFG_OFF 0x90
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#define USB_SBUSCFG_BAWR_OFF 0x6
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#define USB_SBUSCFG_BARD_OFF 0x3
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#define USB_SBUSCFG_AHBBRST_OFF 0x0
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#define USB_SBUSCFG_BAWR_ALIGN_64B 0x4
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#define USB_SBUSCFG_BARD_ALIGN_64B 0x4
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#define USB_SBUSCFG_AHBBRST_INCR16 0x7
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/*
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* USB 2.0 Bridge Address Decoding registers setup
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*/
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#ifdef CONFIG_DM_USB
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struct ehci_mvebu_priv {
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struct ehci_ctrl ehci;
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fdt_addr_t hcd_base;
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};
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/*
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* Once all the older Marvell SoC's (Orion, Kirkwood) are converted
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* to the common mvebu archticture including the mbus setup, this
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* will be the only function needed to configure the access windows
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*/
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static void usb_brg_adrdec_setup(void *base)
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{
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const struct mbus_dram_target_info *dram;
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int i;
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dram = mvebu_mbus_dram_info();
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for (i = 0; i < 4; i++) {
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writel(0, base + USB_WINDOW_CTRL(i));
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writel(0, base + USB_WINDOW_BASE(i));
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}
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for (i = 0; i < dram->num_cs; i++) {
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const struct mbus_dram_window *cs = dram->cs + i;
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/* Write size, attributes and target id to control register */
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writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
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(dram->mbus_dram_target_id << 4) | 1,
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base + USB_WINDOW_CTRL(i));
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/* Write base address to base register */
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writel(cs->base, base + USB_WINDOW_BASE(i));
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}
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}
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static void marvell_ehci_powerup_fixup(struct ehci_ctrl *ctrl,
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uint32_t *status_reg, uint32_t *reg)
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{
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struct ehci_mvebu_priv *priv = ctrl->priv;
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/*
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* Set default value for reg SBUSCFG, which is Control for the AMBA
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* system bus interface:
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* BAWR = BARD = 4 : Align rd/wr bursts packets larger than 64 bytes
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* AHBBRST = 7 : Align AHB burst for packets larger than 64 bytes
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*/
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writel((USB_SBUSCFG_BAWR_ALIGN_64B << USB_SBUSCFG_BAWR_OFF) |
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(USB_SBUSCFG_BARD_ALIGN_64B << USB_SBUSCFG_BARD_OFF) |
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(USB_SBUSCFG_AHBBRST_INCR16 << USB_SBUSCFG_AHBBRST_OFF),
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priv->hcd_base + USB2_SBUSCFG_OFF);
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mdelay(50);
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}
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static struct ehci_ops marvell_ehci_ops = {
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.powerup_fixup = NULL,
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};
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static int ehci_mvebu_probe(struct udevice *dev)
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{
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struct ehci_mvebu_priv *priv = dev_get_priv(dev);
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struct ehci_hccr *hccr;
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struct ehci_hcor *hcor;
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/*
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* Get the base address for EHCI controller from the device node
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*/
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priv->hcd_base = dev_get_addr(dev);
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if (priv->hcd_base == FDT_ADDR_T_NONE) {
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debug("Can't get the EHCI register base address\n");
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return -ENXIO;
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}
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/*
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* For SoCs without hlock like Armada3700 we need to program the sbuscfg
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* reg to guarantee AHB master's burst will not overrun or underrun
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* the FIFO. Otherwise all USB2 write option will fail.
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* Also, the address decoder doesn't need to get setup with this
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* SoC, so don't call usb_brg_adrdec_setup().
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*/
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if (of_device_is_compatible(dev, "marvell,armada3700-ehci"))
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marvell_ehci_ops.powerup_fixup = marvell_ehci_powerup_fixup;
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else
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usb_brg_adrdec_setup((void *)priv->hcd_base);
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hccr = (struct ehci_hccr *)(priv->hcd_base + 0x100);
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hcor = (struct ehci_hcor *)
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((uintptr_t)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
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debug("ehci-marvell: init hccr %lx and hcor %lx hc_length %ld\n",
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(uintptr_t)hccr, (uintptr_t)hcor,
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(uintptr_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
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return ehci_register(dev, hccr, hcor, &marvell_ehci_ops, 0,
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USB_INIT_HOST);
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}
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static const struct udevice_id ehci_usb_ids[] = {
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{ .compatible = "marvell,orion-ehci", },
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{ .compatible = "marvell,armada3700-ehci", },
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{ }
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};
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U_BOOT_DRIVER(ehci_mvebu) = {
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.name = "ehci_mvebu",
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.id = UCLASS_USB,
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.of_match = ehci_usb_ids,
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.probe = ehci_mvebu_probe,
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.remove = ehci_deregister,
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.ops = &ehci_usb_ops,
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.platdata_auto_alloc_size = sizeof(struct usb_platdata),
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.priv_auto_alloc_size = sizeof(struct ehci_mvebu_priv),
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.flags = DM_FLAG_ALLOC_PRIV_DMA,
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};
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#else
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#define MVUSB_BASE(port) MVUSB0_BASE
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static void usb_brg_adrdec_setup(int index)
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{
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int i;
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u32 size, base, attrib;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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/* Enable DRAM bank */
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switch (i) {
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case 0:
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attrib = MVUSB0_CPU_ATTR_DRAM_CS0;
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break;
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case 1:
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attrib = MVUSB0_CPU_ATTR_DRAM_CS1;
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break;
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case 2:
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attrib = MVUSB0_CPU_ATTR_DRAM_CS2;
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break;
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case 3:
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attrib = MVUSB0_CPU_ATTR_DRAM_CS3;
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break;
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default:
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/* invalide bank, disable access */
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attrib = 0;
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break;
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}
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size = gd->bd->bi_dram[i].size;
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base = gd->bd->bi_dram[i].start;
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if ((size) && (attrib))
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writel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
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attrib, MVCPU_WIN_ENABLE),
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MVUSB0_BASE + USB_WINDOW_CTRL(i));
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else
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writel(MVCPU_WIN_DISABLE,
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MVUSB0_BASE + USB_WINDOW_CTRL(i));
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writel(base, MVUSB0_BASE + USB_WINDOW_BASE(i));
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}
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}
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/*
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* Create the appropriate control structures to manage
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* a new EHCI host controller.
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*/
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int ehci_hcd_init(int index, enum usb_init_type init,
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struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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usb_brg_adrdec_setup(index);
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*hccr = (struct ehci_hccr *)(MVUSB_BASE(index) + 0x100);
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*hcor = (struct ehci_hcor *)((uint32_t) *hccr
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+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
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debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n",
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(uint32_t)*hccr, (uint32_t)*hcor,
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(uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
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return 0;
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}
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/*
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* Destroy the appropriate control structures corresponding
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* the the EHCI host controller.
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*/
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int ehci_hcd_stop(int index)
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{
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return 0;
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}
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#endif /* CONFIG_DM_USB */
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