mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
c99512d6bd
Both CFG_PCISPEED_66 and CFG_IPBSPEED_133 are misnamed, as defining them does not cause PCI or IPB clocks to run at the specified speed. Instead, they configure divisors used to calculate said clocks. This patch renames the defines according to their real function. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Acked-by: Bartlomiej Sieka <tur@semihalf.com>
400 lines
12 KiB
C
400 lines
12 KiB
C
/*
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* (C) Copyright 2003-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*************************************************************************
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* (c) 2005 esd gmbh Hannover
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*
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*
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* from IceCube.h file
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* by Reinhard Arlt reinhard.arlt@esd-electronics.com
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*
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*************************************************************************/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */
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#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
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#define CONFIG_ICECUBE 1 /* ... on IceCube board */
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#define CONFIG_PF5200 1 /* ... on PF5200 board */
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#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
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#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* Serial console configuration
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*/
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#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
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#if 0 /* test-only */
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#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
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#else
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#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
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#endif
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
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/*
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* PCI Mapping:
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* 0x40000000 - 0x4fffffff - PCI Memory
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* 0x50000000 - 0x50ffffff - PCI IO Space
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*/
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#define CONFIG_PCI 1
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#define CONFIG_PCI_PNP 1
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#define CONFIG_PCI_SCAN_SHOW 1
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#define CONFIG_PCI_MEM_BUS 0x40000000
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#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
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#define CONFIG_PCI_MEM_SIZE 0x10000000
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#define CONFIG_PCI_IO_BUS 0x50000000
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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#define CONFIG_PCI_IO_SIZE 0x01000000
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#define CONFIG_MII 1
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#if 0 /* test-only !!! */
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#define CONFIG_NET_MULTI 1
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#define CONFIG_EEPRO100 1
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#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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#define CONFIG_NS8382X 1
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#endif
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#define ADD_PCI_CMD CFG_CMD_PCI
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#else /* MPC5100 */
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#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
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#endif
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/* Partitions */
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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/* USB */
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#if 0
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#define CONFIG_USB_OHCI
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#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
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#define CONFIG_USB_STORAGE
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#else
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#define ADD_USB_CMD 0
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#endif
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/*
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* Supported commands
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*/
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
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CFG_CMD_EEPROM | \
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CFG_CMD_FAT | \
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CFG_CMD_I2C | \
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CFG_CMD_IDE | \
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CFG_CMD_BSP | \
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CFG_CMD_ELF | \
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ADD_PCI_CMD )
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
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# define CFG_LOWBOOT 1
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# define CFG_LOWBOOT16 1
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#endif
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#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
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# define CFG_LOWBOOT 1
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# define CFG_LOWBOOT08 1
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#endif
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/*
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* Autobooting
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*/
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#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
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#define CONFIG_PREBOOT "echo;" \
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"echo Welcome to ParaFinder pf5200;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
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"flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
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"net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
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"vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
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"ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
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"loadaddr=01000000\0" \
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"serverip=192.168.2.99\0" \
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"gatewayip=10.0.0.79\0" \
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"user=mu\0" \
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"target=pf5200.esd\0" \
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"script=pf5200.bat\0" \
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"image=/tftpboot/vxWorks_pf5200\0" \
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"ipaddr=10.0.13.196\0" \
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"netmask=255.255.0.0\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
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#if defined(CONFIG_MPC5200)
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/*
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* IPB Bus clocking configuration.
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*/
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#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
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#endif
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/*
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* I2C configuration
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*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
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#define CFG_I2C_SPEED 86000 /* 100 kHz */
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#define CFG_I2C_SLAVE 0x7F
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/*
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* EEPROM configuration
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*/
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#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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#define CFG_EEPROM_PAGE_WRITE_BITS 5
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
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#define CFG_I2C_MULTI_EEPROMS 1
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/*
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* Flash configuration
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*/
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#define CFG_FLASH_BASE 0xFE000000
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#define CFG_FLASH_SIZE 0x02000000
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#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00000000)
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#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
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#define CFG_MAX_FLASH_SECT 512
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#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
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/*
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* Environment settings
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*/
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#if 1 /* test-only */
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#define CFG_ENV_IS_IN_FLASH 0
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#define CFG_ENV_SIZE 0x10000
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#define CFG_ENV_SECT_SIZE 0x10000
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#define CONFIG_ENV_OVERWRITE 1
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#else
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#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
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#define CFG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
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#define CFG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */
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/* total size of a CAT24WC32 is 8192 bytes */
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#define CONFIG_ENV_OVERWRITE 1
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#endif
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/*
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* Memory map
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*/
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#define CFG_MBAR 0xF0000000
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_DEFAULT_MBAR 0x80000000
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/* Use SRAM until RAM will be available */
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#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
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#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_MONITOR_BASE TEXT_BASE
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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# define CFG_RAMBOOT 1
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#endif
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#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*
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* Ethernet configuration
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*/
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#define CONFIG_MPC5xxx_FEC 1
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/*
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* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
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*/
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/* #define CONFIG_FEC_10MBIT 1 */
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#define CONFIG_PHY_ADDR 0x00
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#define CONFIG_UDP_CHECKSUM 1
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/*
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* GPIO configuration
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*/
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#define CFG_GPS_PORT_CONFIG 0x01052444
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
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/*
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* Various low-level settings
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*/
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#if defined(CONFIG_MPC5200)
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#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
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#define CFG_HID0_FINAL HID0_ICE
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#else
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#define CFG_HID0_INIT 0
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#define CFG_HID0_FINAL 0
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#endif
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#define CFG_BOOTCS_START CFG_FLASH_BASE
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#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
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#define CFG_BOOTCS_CFG 0x0004DD00
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#define CFG_CS0_START CFG_FLASH_BASE
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#define CFG_CS0_SIZE CFG_FLASH_SIZE
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#define CFG_CS1_START 0xfd000000
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#define CFG_CS1_SIZE 0x00010000
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#define CFG_CS1_CFG 0x10101410
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#define CFG_CS_BURST 0x00000000
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#define CFG_CS_DEADCYCLE 0x33333333
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#define CFG_RESET_ADDRESS 0xff000000
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/*-----------------------------------------------------------------------
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* USB stuff
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_USB_CLOCK 0x0001BBBB
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#define CONFIG_USB_CONFIG 0x00001000
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff Supports IDE harddisk
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*-----------------------------------------------------------------------
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*/
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#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
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#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
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#undef CONFIG_IDE_LED /* LED for ide not supported */
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#define CONFIG_IDE_RESET /* reset for ide supported */
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#define CONFIG_IDE_PREINIT
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#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
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#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
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#define CFG_ATA_IDE0_OFFSET 0x0000
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#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
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/* Offset for data I/O */
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#define CFG_ATA_DATA_OFFSET (0x0060)
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/* Offset for normal register accesses */
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#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
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/* Offset for alternate registers */
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#define CFG_ATA_ALT_OFFSET (0x005C)
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/* Interval between registers */
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#define CFG_ATA_STRIDE 4
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/*-----------------------------------------------------------------------
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* CPLD stuff
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*/
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#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
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#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
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/* CPLD program pin configuration */
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#define CFG_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */
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#define CFG_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */
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#define CFG_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */
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#define CFG_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */
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#define JTAG_GPIO_ADDR_TMS (CFG_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */
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#define JTAG_GPIO_ADDR_TCK (CFG_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */
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#define JTAG_GPIO_ADDR_TDI (CFG_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */
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#define JTAG_GPIO_ADDR_TDO (CFG_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */
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#define JTAG_GPIO_ADDR_CFG (CFG_MBAR + 0xB00)
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#define JTAG_GPIO_CFG_SET 0x00000000
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#define JTAG_GPIO_CFG_RESET 0x00F00000
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#define JTAG_GPIO_ADDR_EN_TMS (CFG_MBAR + 0xB04)
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#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */
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#define JTAG_GPIO_TMS_EN_RESET 0x00000000
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#define JTAG_GPIO_ADDR_DDR_TMS (CFG_MBAR + 0xB0C)
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#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */
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#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
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#define JTAG_GPIO_ADDR_EN_TCK (CFG_MBAR + 0xC00)
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#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */
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#define JTAG_GPIO_TCK_EN_RESET 0x00000000
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#define JTAG_GPIO_ADDR_DDR_TCK (CFG_MBAR + 0xC08)
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#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */
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#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
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#define JTAG_GPIO_ADDR_EN_TDI (CFG_MBAR + 0xC00)
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#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */
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#define JTAG_GPIO_TDI_EN_RESET 0x00000000
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#define JTAG_GPIO_ADDR_DDR_TDI (CFG_MBAR + 0xC08)
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#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */
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#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
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#define JTAG_GPIO_ADDR_EN_TDO (CFG_MBAR + 0xB04)
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#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */
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#define JTAG_GPIO_TDO_EN_RESET 0x00000000
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#define JTAG_GPIO_ADDR_DDR_TDO (CFG_MBAR + 0xB0C)
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#define JTAG_GPIO_TDO_DDR_SET 0x00000000
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#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */
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#endif /* __CONFIG_H */
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