mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
c99512d6bd
Both CFG_PCISPEED_66 and CFG_IPBSPEED_133 are misnamed, as defining them does not cause PCI or IPB clocks to run at the specified speed. Instead, they configure divisors used to calculate said clocks. This patch renames the defines according to their real function. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Acked-by: Bartlomiej Sieka <tur@semihalf.com>
416 lines
12 KiB
C
416 lines
12 KiB
C
/*
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* (C) Copyright 2003-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004
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* Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* Check valid setting of revision define.
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* Total5100 and Total5200 Rev.1 are identical except for the processor.
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*/
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#if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2)
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#error CONFIG_TOTAL5200_REV must be 1 or 2
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#endif
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
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#define CONFIG_TOTAL5200 1 /* ... on Total5200 board */
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#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* Serial console configuration
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*/
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#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
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#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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/*
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* Video console
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*/
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#if 1
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#define CONFIG_VIDEO
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#define CONFIG_VIDEO_SED13806
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#define CONFIG_VIDEO_SED13806_16BPP
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VIDEO_LOGO
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/* #define CONFIG_VIDEO_BMP_LOGO */
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#define CONFIG_CONSOLE_EXTRA_INFO
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#define CONFIG_VIDEO_SW_CURSOR
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#define CONFIG_SPLASH_SCREEN
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#define ADD_VIDEO_CMD CFG_CMD_BMP
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#else
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#define ADD_VIDEO_CMD 0
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#endif
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#ifdef CONFIG_MPC5200 /* MGT5100 PCI is not supported yet. */
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/*
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* PCI Mapping:
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* 0x40000000 - 0x4fffffff - PCI Memory
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* 0x50000000 - 0x50ffffff - PCI IO Space
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*/
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#define CONFIG_PCI 1
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#define CONFIG_PCI_PNP 1
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#define CONFIG_PCI_SCAN_SHOW 1
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#define CONFIG_PCI_MEM_BUS 0x40000000
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#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
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#define CONFIG_PCI_MEM_SIZE 0x10000000
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#define CONFIG_PCI_IO_BUS 0x50000000
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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#define CONFIG_PCI_IO_SIZE 0x01000000
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#define CONFIG_NET_MULTI 1
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#define CONFIG_MII 1
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#define CONFIG_EEPRO100 1
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#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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#define CONFIG_NS8382X 1
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#define ADD_PCI_CMD CFG_CMD_PCI
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#else /* MGT5100 */
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#define CONFIG_MII 1
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#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
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#endif
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/* Partitions */
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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/* USB */
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#if 1
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#define CONFIG_USB_OHCI
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#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
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#define CONFIG_USB_STORAGE
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#else
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#define ADD_USB_CMD 0
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#endif
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/*
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* Supported commands
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*/
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
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CFG_CMD_PING | \
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CFG_CMD_I2C | \
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CFG_CMD_EEPROM | \
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CFG_CMD_FAT | \
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CFG_CMD_IDE | \
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ADD_VIDEO_CMD | \
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ADD_PCI_CMD | \
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ADD_USB_CMD)
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#if (TEXT_BASE == 0xFE000000) /* Boot low */
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# define CFG_LOWBOOT 1
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#endif
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/*
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* Autobooting
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*/
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_PREBOOT \
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"setenv stdout serial;setenv stderr serial;" \
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"echo;" \
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"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"flash_nfs=run nfsargs addip;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
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"rootpath=/opt/eldk/ppc_82xx\0" \
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"bootfile=/tftpboot/MPC5200/uImage\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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#if defined(CONFIG_MPC5200)
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/*
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* IPB Bus clocking configuration.
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*/
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#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
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#endif
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/*
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* I2C configuration
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*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */
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#define CFG_I2C_SPEED 100000 /* 100 kHz */
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#define CFG_I2C_SLAVE 0x7F
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/*
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* EEPROM configuration
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*/
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#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
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#define CFG_I2C_EEPROM_ADDR_LEN 1
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#define CFG_EEPROM_PAGE_WRITE_BITS 3
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
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/*
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* Flash configuration
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*/
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#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
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#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
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#if CONFIG_TOTAL5200_REV==2
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# define CFG_MAX_FLASH_BANKS 3 /* max num of flash banks */
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# define CFG_FLASH_BANKS_LIST { CFG_CS5_START, CFG_CS4_START, CFG_BOOTCS_START }
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#else
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# define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
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# define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
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#endif
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#define CFG_FLASH_EMPTY_INFO
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#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
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#if CONFIG_TOTAL5200_REV==1
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# define CFG_FLASH_BASE 0xFE000000
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# define CFG_FLASH_SIZE 0x02000000
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#elif CONFIG_TOTAL5200_REV==2
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# define CFG_FLASH_BASE 0xFA000000
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# define CFG_FLASH_SIZE 0x06000000
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#endif /* CONFIG_TOTAL5200_REV */
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#if defined(CFG_LOWBOOT)
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# define CFG_ENV_ADDR 0xFE040000
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#else /* CFG_LOWBOOT */
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# define CFG_ENV_ADDR 0xFFF40000
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#endif /* CFG_LOWBOOT */
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/*
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* Environment settings
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*/
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_SIZE 0x40000
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#define CFG_ENV_SECT_SIZE 0x40000
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#define CONFIG_ENV_OVERWRITE 1
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/*
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* Memory map
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_DEFAULT_MBAR 0x80000000
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#define CFG_MBAR 0xF0000000 /* 64 kB */
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#define CFG_FPGA_BASE 0xF0010000 /* 64 kB */
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#define CFG_CPLD_BASE 0xF0020000 /* 64 kB */
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#define CFG_LCD_BASE 0xF1000000 /* 4096 kB */
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/* Use SRAM until RAM will be available */
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#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
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#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_MONITOR_BASE TEXT_BASE
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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# define CFG_RAMBOOT 1
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#endif
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#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*
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* Ethernet configuration
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*/
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#define CONFIG_MPC5xxx_FEC 1
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/* dummy, 7-wire FEC does not have phy address */
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#define CONFIG_PHY_ADDR 0x00
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/*
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* GPIO configuration
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*
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* CS1: SDRAM CS1 disabled, gpio_wkup_6 enabled 0
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* Reserved 0
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* ALTs: CAN1/2 on PSC2, SPI on PSC3 00
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* CS7: Interrupt GPIO on PSC3_5 0
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* CS8: Interrupt GPIO on PSC3_4 0
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* ATA: reset default, changed in ATA driver 00
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* IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO 0
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* IRDA: reset default, changed in IrDA driver 000
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* ETHER: reset default, changed in Ethernet driver 0000
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* PCI_DIS: reset default, changed in PCI driver 0
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* USB_SE: reset default, changed in USB driver 0
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* USB: reset default, changed in USB driver 00
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* PSC3: SPI and UART functionality without CD 1100
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* Reserved 0
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* PSC2: CAN1/2 001
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* Reserved 0
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* PSC1: reset default, changed in AC'97 driver 000
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*
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*/
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#define CFG_GPS_PORT_CONFIG 0x00000C10
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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/*
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* Various low-level settings
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*/
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#if defined(CONFIG_MPC5200)
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#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
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#define CFG_HID0_FINAL HID0_ICE
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#else
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#define CFG_HID0_INIT 0
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#define CFG_HID0_FINAL 0
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#endif
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#if defined (CONFIG_MGT5100)
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# define CONFIG_BOARD_EARLY_INIT_R /* switch from CS_BOOT to CS0 */
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#endif
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#if CONFIG_TOTAL5200_REV==1
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# define CFG_BOOTCS_START CFG_FLASH_BASE
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# define CFG_BOOTCS_SIZE 0x02000000 /* 32 MB */
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# define CFG_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
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# define CFG_CS0_START CFG_FLASH_BASE
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# define CFG_CS0_SIZE 0x02000000 /* 32 MB */
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#else
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# define CFG_BOOTCS_START (CFG_CS4_START + CFG_CS4_SIZE)
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# define CFG_BOOTCS_SIZE 0x02000000 /* 32 MB */
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# define CFG_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
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# define CFG_CS4_START (CFG_CS5_START + CFG_CS5_SIZE)
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# define CFG_CS4_SIZE 0x02000000 /* 32 MB */
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# define CFG_CS4_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
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# define CFG_CS5_START CFG_FLASH_BASE
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# define CFG_CS5_SIZE 0x02000000 /* 32 MB */
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# define CFG_CS5_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
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#endif
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#define CFG_CS1_START CFG_FPGA_BASE
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#define CFG_CS1_SIZE 0x00010000 /* 64 kB */
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#define CFG_CS1_CFG 0x0019FF00 /* 25WS, MX, AL, AA, CE, AS_25, DS_32 */
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#define CFG_CS2_START CFG_LCD_BASE
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#define CFG_CS2_SIZE 0x00400000 /* 4096 kB */
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#define CFG_CS2_CFG 0x0032FD0C /* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */
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#if CONFIG_TOTAL5200_REV==1
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# define CFG_CS3_START CFG_CPLD_BASE
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# define CFG_CS3_SIZE 0x00010000 /* 64 kB */
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# define CFG_CS3_CFG 0x000ADF00 /* 10WS, MX, AL, CE, AS_25, DS_32 */
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#else
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# define CFG_CS3_START CFG_CPLD_BASE
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# define CFG_CS3_SIZE 0x00010000 /* 64 kB */
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# define CFG_CS3_CFG 0x000AD800 /* 10WS, MX, AL, CE, AS_24, DS_8 */
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#endif
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#define CFG_CS_BURST 0x00000000
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#define CFG_CS_DEADCYCLE 0x33333333
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/*-----------------------------------------------------------------------
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* USB stuff
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_USB_CLOCK 0x0001BBBB
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#define CONFIG_USB_CONFIG 0x00001000
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff Supports IDE harddisk
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*-----------------------------------------------------------------------
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*/
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#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
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#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
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#undef CONFIG_IDE_LED /* LED for ide not supported */
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#define CONFIG_IDE_RESET /* reset for ide supported */
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#define CONFIG_IDE_PREINIT
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#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
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#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
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#define CFG_ATA_IDE0_OFFSET 0x0000
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#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
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/* Offset for data I/O */
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#define CFG_ATA_DATA_OFFSET (0x0060)
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/* Offset for normal register accesses */
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#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
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/* Offset for alternate registers */
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#define CFG_ATA_ALT_OFFSET (0x005C)
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/* Interval between registers */
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#define CFG_ATA_STRIDE 4
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#endif /* __CONFIG_H */
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