mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
700a0c648d
Old, obsolete and duplicated code was cleaned up and replace by the new partitioning method. There are two possible approaches now: * define a single, static partition * use mtdparts command line option and dynamic partitioning Default is static partitioning.
566 lines
18 KiB
C
566 lines
18 KiB
C
/*
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* (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
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* Stephan Linz <linz@li-pro.net>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/***********************************************************************
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* Include the whole NIOS CPU configuration.
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*
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* !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!!
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*
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***********************************************************************/
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#if defined(CONFIG_NIOS_SAFE_32)
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#include <configs/DK1S10_safe_32.h>
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#elif defined(CONFIG_NIOS_STANDARD_32)
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#include <configs/DK1S10_standard_32.h>
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#elif defined(CONFIG_NIOS_MTX_LDK_20)
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#include <configs/DK1S10_mtx_ldk_20.h>
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#else
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#error *** CFG_ERROR: you have to setup right NIOS CPU configuration
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#endif
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/*------------------------------------------------------------------------
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* BOARD/CPU -- TOP-LEVEL
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*----------------------------------------------------------------------*/
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#define CONFIG_NIOS 1 /* NIOS-32 core */
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#define CONFIG_DK1S10 1 /* Stratix DK-1S10 board*/
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#define CONFIG_SYS_CLK_FREQ CFG_NIOS_CPU_CLK/* 50 MHz core clock */
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#define CFG_HZ 1000 /* 1 msec time tick */
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#undef CFG_CLKS_IN_HZ
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
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/*------------------------------------------------------------------------
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* BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
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*----------------------------------------------------------------------*/
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#if (CFG_NIOS_CPU_SDRAM_SIZE != 0)
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#define CFG_SDRAM_BASE CFG_NIOS_CPU_SDRAM_BASE
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#define CFG_SDRAM_SIZE CFG_NIOS_CPU_SDRAM_SIZE
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#else
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#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
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#endif
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#if defined(CFG_NIOS_CPU_SRAM_BASE) && defined(CFG_NIOS_CPU_SRAM_SIZE)
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#define CFG_SRAM_BASE CFG_NIOS_CPU_SRAM_BASE
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#define CFG_SRAM_SIZE CFG_NIOS_CPU_SRAM_SIZE
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#else
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#undef CFG_SRAM_BASE
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#undef CFG_SRAM_SIZE
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#endif
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#define CFG_VECT_BASE CFG_NIOS_CPU_VEC_BASE
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/*------------------------------------------------------------------------
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* MEMORY ORGANIZATION - For the most part, you can put things pretty
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* much anywhere. This is pretty flexible for Nios. So here we make some
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* arbitrary choices & assume that the monitor is placed at the end of
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* a memory resource (so you must make sure TEXT_BASE is chosen
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* appropriately).
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*
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* -The heap is placed below the monitor.
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* -Global data is placed below the heap.
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* -The stack is placed below global data (&grows down).
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*----------------------------------------------------------------------*/
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */
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#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/
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#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
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#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP CFG_GBL_DATA_OFFSET
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/*------------------------------------------------------------------------
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* FLASH (AM29LV065D)
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*----------------------------------------------------------------------*/
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#if (CFG_NIOS_CPU_FLASH_SIZE != 0)
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#define CFG_FLASH_BASE CFG_NIOS_CPU_FLASH_BASE
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#define CFG_FLASH_SIZE CFG_NIOS_CPU_FLASH_SIZE
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#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */
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#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */
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#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
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#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
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#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */
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#else
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#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
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#endif
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/*------------------------------------------------------------------------
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* ENVIRONMENT
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*----------------------------------------------------------------------*/
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#if (CFG_NIOS_CPU_FLASH_SIZE != 0)
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#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */
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#if defined(CONFIG_NIOS_STANDARD_32)
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#define CFG_ENV_ADDR CFG_FLASH_BASE /* Mem addr of env */
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#elif defined(CONFIG_NIOS_MTX_LDK_20)
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#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
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#else
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#error *** CFG_ERROR: you have to setup the environment base address CFG_ENV_ADDR
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#endif
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#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
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#define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */
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#else
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#define CFG_ENV_IS_NOWHERE 1 /* NO Environment */
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#endif
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/*------------------------------------------------------------------------
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* CONSOLE
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*----------------------------------------------------------------------*/
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#if (CFG_NIOS_CPU_UART_NUMS != 0)
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#define CFG_NIOS_CONSOLE CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#if (CFG_NIOS_CPU_UART0_BR != 0)
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#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
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#define CONFIG_BAUDRATE CFG_NIOS_CPU_UART0_BR
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#else
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#undef CFG_NIOS_FIXEDBAUD
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#define CONFIG_BAUDRATE 115200
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#endif
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#else
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#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
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#endif
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/*------------------------------------------------------------------------
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* TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT,
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* so an avalon bus timer is required.
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*----------------------------------------------------------------------*/
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#if (CFG_NIOS_CPU_TIMER_NUMS != 0) && defined(CFG_NIOS_CPU_TICK_TIMER)
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#if (CFG_NIOS_CPU_TICK_TIMER == 0)
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#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick */
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#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER0_IRQ
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#if (CFG_NIOS_CPU_TIMER0_FP == 1) /* fixed period */
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#if (CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ)
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#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER0_PER / CFG_HZ)
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#else
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#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
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#endif
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#undef CFG_NIOS_TMRCNT /* no preloadable counter value */
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#elif (CFG_NIOS_CPU_TIMER0_FP == 0) /* variable period */
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#if (CFG_HZ <= 1000)
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#define CFG_NIOS_TMRMS (1000 / CFG_HZ)
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#else
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#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
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#endif
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#define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ)
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#else
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#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct
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#endif
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#elif (CFG_NIOS_CPU_TICK_TIMER == 1)
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#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick */
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#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER1_IRQ
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#if (CFG_NIOS_CPU_TIMER1_FP == 1) /* fixed period */
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#if (CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
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#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
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#else
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#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
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#endif
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#undef CFG_NIOS_TMRCNT /* no preloadable counter value */
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#elif (CFG_NIOS_CPU_TIMER1_FP == 0) /* variable period */
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#if (CFG_HZ <= 1000)
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#define CFG_NIOS_TMRMS (1000 / CFG_HZ)
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#else
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#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
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#endif
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#define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ)
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#else
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#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct
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#endif
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#endif /* CFG_NIOS_CPU_TICK_TIMER */
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#else
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#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
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#endif
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/*------------------------------------------------------------------------
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* Ethernet -- needs work!
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*----------------------------------------------------------------------*/
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#if (CFG_NIOS_CPU_LAN_NUMS == 1)
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#if (CFG_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */
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#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
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#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
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#define CONFIG_SMC91111_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
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#if (CFG_NIOS_CPU_LAN0_BUSW == 32)
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#define CONFIG_SMC_USE_32_BIT 1
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#else /* no */
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#undef CONFIG_SMC_USE_32_BIT
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#endif
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#elif (CFG_NIOS_CPU_LAN0_TYPE == 1) /* CS8900A */
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/********************************************/
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/* !!! CS8900 is __not__ tested on NIOS !!! */
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/********************************************/
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#define CONFIG_DRIVER_CS8900 /* Using CS8900 */
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#define CS8900_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
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#if (CFG_NIOS_CPU_LAN0_BUSW == 32)
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#undef CS8900_BUS16
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#define CS8900_BUS32 1
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#else /* no */
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#define CS8900_BUS16 1
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#undef CS8900_BUS32
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#endif
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#else
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#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config
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#endif
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#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_IPADDR 192.168.2.21
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#define CONFIG_SERVERIP 192.168.2.16
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#else
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#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h
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#endif
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/*------------------------------------------------------------------------
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* STATUS LEDs
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*----------------------------------------------------------------------*/
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#if (CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_LED_PIO)
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#if (CFG_NIOS_CPU_LED_PIO == 0)
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#error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h
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#elif (CFG_NIOS_CPU_LED_PIO == 1)
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#error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h
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#elif (CFG_NIOS_CPU_LED_PIO == 2)
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#define STATUS_LED_BASE CFG_NIOS_CPU_PIO2
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#define STATUS_LED_BITS CFG_NIOS_CPU_PIO2_BITS
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#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
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#if (CFG_NIOS_CPU_PIO2_TYPE == 1)
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#define STATUS_LED_WRONLY 1
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#else
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#undef STATUS_LED_WRONLY
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#endif
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#elif (CFG_NIOS_CPU_LED_PIO == 3)
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#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h
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#elif (CFG_NIOS_CPU_LED_PIO == 4)
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#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
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#elif (CFG_NIOS_CPU_LED_PIO == 5)
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#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
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#elif (CFG_NIOS_CPU_LED_PIO == 6)
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#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
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#elif (CFG_NIOS_CPU_LED_PIO == 7)
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#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
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#elif (CFG_NIOS_CPU_LED_PIO == 8)
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#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
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#elif (CFG_NIOS_CPU_LED_PIO == 9)
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#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
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#else
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#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case
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#endif
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#define CONFIG_STATUS_LED 1 /* enable status led driver */
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#define STATUS_LED_BIT (1 << 0) /* LED[0] */
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#define STATUS_LED_STATE STATUS_LED_BLINKING
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#define STATUS_LED_BOOT_STATE STATUS_LED_OFF
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#define STATUS_LED_PERIOD (CFG_HZ / 10) /* ca. 1 Hz */
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#define STATUS_LED_BOOT 0 /* boot LED */
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#if (STATUS_LED_BITS > 1)
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#define STATUS_LED_BIT1 (1 << 1) /* LED[1] */
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#define STATUS_LED_STATE1 STATUS_LED_OFF
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#define STATUS_LED_PERIOD1 (CFG_HZ / 50) /* ca. 5 Hz */
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#define STATUS_LED_RED 1 /* fail LED */
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#endif
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#if (STATUS_LED_BITS > 2)
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#define STATUS_LED_BIT2 (1 << 2) /* LED[2] */
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#define STATUS_LED_STATE2 STATUS_LED_OFF
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#define STATUS_LED_PERIOD2 (CFG_HZ / 10) /* ca. 1 Hz */
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#define STATUS_LED_YELLOW 2 /* info LED */
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#endif
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#if (STATUS_LED_BITS > 3)
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#define STATUS_LED_BIT3 (1 << 3) /* LED[3] */
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#define STATUS_LED_STATE3 STATUS_LED_OFF
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#define STATUS_LED_PERIOD3 (CFG_HZ / 10) /* ca. 1 Hz */
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#define STATUS_LED_GREEN 3 /* info LED */
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#endif
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#define STATUS_LED_PAR 1 /* makes status_led.h happy */
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#endif /* CFG_NIOS_CPU_PIO_NUMS */
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/*------------------------------------------------------------------------
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* SEVEN SEGMENT LED DISPLAY
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*----------------------------------------------------------------------*/
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#if (CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_SEVENSEG_PIO)
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#if (CFG_NIOS_CPU_SEVENSEG_PIO == 0)
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#error *** CFG_ERROR: seven segment display at PIO0 not supported, expand your config.h
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#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 1)
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#error *** CFG_ERROR: seven segment display at PIO1 not supported, expand your config.h
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#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 2)
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#error *** CFG_ERROR: seven segment display at PIO2 not supported, expand your config.h
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#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 3)
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#define SEVENSEG_BASE CFG_NIOS_CPU_PIO3
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#define SEVENSEG_BITS CFG_NIOS_CPU_PIO3_BITS
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#define SEVENSEG_ACTIVE 0 /* LED on for bit == 1 */
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#if (CFG_NIOS_CPU_PIO3_TYPE == 1)
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#define SEVENSEG_WRONLY 1
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#else
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#undef SEVENSEG_WRONLY
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#endif
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#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 4)
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#error *** CFG_ERROR: seven segment display at PIO4 not supported, expand your config.h
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#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 5)
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#error *** CFG_ERROR: seven segment display at PIO5 not supported, expand your config.h
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#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 6)
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#error *** CFG_ERROR: seven segment display at PIO6 not supported, expand your config.h
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#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 7)
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#error *** CFG_ERROR: seven segment display at PIO7 not supported, expand your config.h
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#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 8)
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#error *** CFG_ERROR: seven segment display at PIO8 not supported, expand your config.h
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#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 9)
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#error *** CFG_ERROR: seven segment display at PIO9 not supported, expand your config.h
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#else
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#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case
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#endif
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#define CONFIG_SEVENSEG 1 /* enable seven segment led driver */
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/*
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* Dual 7-Segment Display pin assignment -- read more in your
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* "Nios Development Board Reference Manual"
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*
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*
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* (U8) HI:D[15..8] (U9) LO:D[7..0]
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* ______ ______
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* | D14 | | D6 |
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* | | | |
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* D9| |D13 D1| |D5
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* |______| |______| ___
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* | D8 | | D0 | | A |
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* | | | | F|___|B
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* D10| |D12 D2| |D4 | G |
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* |______| |______| E|___|C
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* D11 * D3 * D *
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* D15 D7 DP
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*
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*/
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#define SEVENSEG_DIGIT_HI_LO_EQUAL 1 /* high nibble equal low nibble */
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#define SEVENSEG_DIGIT_A (1 << 6) /* bit 6 is segment A */
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#define SEVENSEG_DIGIT_B (1 << 5) /* bit 5 is segment B */
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#define SEVENSEG_DIGIT_C (1 << 4) /* bit 4 is segment C */
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#define SEVENSEG_DIGIT_D (1 << 3) /* bit 3 is segment D */
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#define SEVENSEG_DIGIT_E (1 << 2) /* bit 2 is segment E */
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#define SEVENSEG_DIGIT_F (1 << 1) /* bit 1 is segment F */
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#define SEVENSEG_DIGIT_G (1 << 0) /* bit 0 is segment G */
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#define SEVENSEG_DIGIT_DP (1 << 7) /* bit 7 is decimal point */
|
|
|
|
#endif /* CFG_NIOS_CPU_PIO_NUMS */
|
|
|
|
/*------------------------------------------------------------------------
|
|
* COMMANDS
|
|
*----------------------------------------------------------------------*/
|
|
#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
|
|
CFG_CMD_ASKENV | \
|
|
CFG_CMD_BEDBUG | \
|
|
CFG_CMD_BMP | \
|
|
CFG_CMD_BSP | \
|
|
CFG_CMD_CACHE | \
|
|
CFG_CMD_DATE | \
|
|
CFG_CMD_DOC | \
|
|
CFG_CMD_DTT | \
|
|
CFG_CMD_EEPROM | \
|
|
CFG_CMD_ELF | \
|
|
CFG_CMD_FAT | \
|
|
CFG_CMD_FDC | \
|
|
CFG_CMD_FDOS | \
|
|
CFG_CMD_HWFLOW | \
|
|
CFG_CMD_IDE | \
|
|
CFG_CMD_I2C | \
|
|
CFG_CMD_JFFS2 | \
|
|
CFG_CMD_KGDB | \
|
|
CFG_CMD_NAND | \
|
|
CFG_CMD_NFS | \
|
|
CFG_CMD_MMC | \
|
|
CFG_CMD_MII | \
|
|
CFG_CMD_PCI | \
|
|
CFG_CMD_PCMCIA | \
|
|
CFG_CMD_SCSI | \
|
|
CFG_CMD_SPI | \
|
|
CFG_CMD_VFD | \
|
|
CFG_CMD_USB | \
|
|
CFG_CMD_XIMG ) )
|
|
|
|
|
|
#include <cmd_confdefs.h>
|
|
|
|
/*------------------------------------------------------------------------
|
|
* KGDB
|
|
*----------------------------------------------------------------------*/
|
|
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
|
#define CONFIG_KGDB_BAUDRATE 9600
|
|
#endif
|
|
|
|
/*------------------------------------------------------------------------
|
|
* MISC
|
|
*----------------------------------------------------------------------*/
|
|
#define CFG_LONGHELP /* undef to save memory */
|
|
#define CFG_PROMPT "DK1S10 > " /* Monitor Command Prompt */
|
|
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
|
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
|
#define CFG_MAXARGS 16 /* max number of command args*/
|
|
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
|
|
|
/* Default load address */
|
|
#if (CFG_SRAM_SIZE != 0)
|
|
|
|
/* default in SRAM */
|
|
#define CFG_LOAD_ADDR CFG_SRAM_BASE
|
|
|
|
#elif (CFG_SDRAM_SIZE != 0)
|
|
|
|
/* default in SDRAM */
|
|
#if (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
|
|
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
|
|
#else
|
|
#define CFG_LOAD_ADDR CFG_SDRAM_BASE
|
|
#endif
|
|
|
|
#else
|
|
#undef CFG_LOAD_ADDR /* force error break */
|
|
#endif
|
|
|
|
|
|
/* MEM test area */
|
|
#if (CFG_SDRAM_SIZE != 0)
|
|
|
|
/* SDRAM begin to stack area (1MB stack) */
|
|
#if (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
|
|
#define CFG_MEMTEST_START (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
|
|
#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024))
|
|
#else
|
|
#define CFG_MEMTEST_START CFG_SDRAM_BASE
|
|
#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024))
|
|
#endif
|
|
|
|
#else
|
|
#undef CFG_MEMTEST_START /* force error break */
|
|
#undef CFG_MEMTEST_END
|
|
#endif
|
|
|
|
/*
|
|
* JFFS2 partitions
|
|
*
|
|
*/
|
|
/* No command line, one static partition, whole device */
|
|
#undef CONFIG_JFFS2_CMDLINE
|
|
#define CONFIG_JFFS2_DEV "nor0"
|
|
#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
|
|
#define CONFIG_JFFS2_PART_OFFSET 0x00000000
|
|
|
|
/* mtdparts command line support */
|
|
/*
|
|
#define CONFIG_JFFS2_CMDLINE
|
|
#define MTDIDS_DEFAULT ""
|
|
#define MTDPARTS_DEFAULT ""
|
|
*/
|
|
|
|
#endif /* __CONFIG_H */
|