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https://github.com/brain-hackers/u-boot-brain
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ee14d29db0
The back-to-bootrom option is rather unfortunately named CONFIG_ROCKCHIP_SPL_BACK_TO_BOOTROM instead of CONFIG_SPL_ROCKCHIP_BACK_TO_BOOTROM To make is selectable through CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BOOTROM), we need to rename it. At the same time, we introduce a TPL_ variant of the option to give us finer-grained control over when it should be used. This change is motivated by our RK3368 boot process, which returns to the boot ROM only from the TPL stage, but not from the SPL stage. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [added fix-up for evb-rk3229_defconfig and phycore-rk3288_defconfig:] [fixed inverted CONFIG_IS_ENABLED test for rk3288:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> include/configs/rock.h: undef
116 lines
3.0 KiB
C
116 lines
3.0 KiB
C
/*
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* (C) Copyright 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_RK3188_COMMON_H
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#define __CONFIG_RK3188_COMMON_H
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#define CONFIG_SYS_CACHELINE_SIZE 64
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#include <asm/arch/hardware.h>
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#include "rockchip-common.h"
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#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_MALLOC_LEN (32 << 20)
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
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#define CONFIG_SYS_TIMER_BASE 0x2000e000 /* TIMER3 */
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#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
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#define CONFIG_SYS_TIMER_COUNTS_DOWN
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#define CONFIG_SYS_NS16550_MEM32
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#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
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/* Bootrom will load u-boot binary to 0x60000000 once return from SPL */
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#define CONFIG_SYS_TEXT_BASE 0x60000000
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#else
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#define CONFIG_SYS_TEXT_BASE 0x60100000
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#endif
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#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
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#define CONFIG_SYS_LOAD_ADDR 0x60800800
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#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800)
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#define CONFIG_ROCKCHIP_CHIP_TAG "RK31"
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#ifdef CONFIG_TPL_BUILD
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#define CONFIG_SPL_TEXT_BASE 0x10080804
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/* tpl size 1kb - 4byte RK31 header */
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#define CONFIG_SPL_MAX_SIZE (0x400 - 0x4)
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#elif defined(CONFIG_SPL_BUILD)
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/* spl size 32kb sram - 2kb bootrom - 1kb spl */
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#define CONFIG_SPL_MAX_SIZE (0x8000 - 0xC00)
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#define CONFIG_SPL_TEXT_BASE 0x10080C00
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#define CONFIG_SPL_FRAMEWORK 1
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#define CONFIG_SPL_CLK 1
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#define CONFIG_SPL_PINCTRL 1
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#define CONFIG_SPL_REGMAP 1
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#define CONFIG_SPL_SYSCON 1
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#define CONFIG_SPL_RAM 1
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#define CONFIG_SPL_DRIVERS_MISC_SUPPORT 1
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#define CONFIG_ROCKCHIP_SERIAL 1
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#endif
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#define CONFIG_SPL_STACK 0x10087fff
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/* MMC/SD IP block */
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#define CONFIG_BOUNCE_BUFFER
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#define CONFIG_SYS_SDRAM_BASE 0x60000000
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#define CONFIG_NR_DRAM_BANKS 1
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#define SDRAM_BANK_SIZE (2UL << 30)
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#define SDRAM_MAX_SIZE 0x80000000
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI
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#define CONFIG_SF_DEFAULT_SPEED 20000000
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#ifndef CONFIG_SPL_BUILD
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/* usb otg */
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#define CONFIG_USB_GADGET
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#define CONFIG_USB_GADGET_DUALSPEED
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#define CONFIG_USB_GADGET_DWC2_OTG
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#define CONFIG_ROCKCHIP_USB2_PHY
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#define CONFIG_USB_GADGET_VBUS_DRAW 0
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#define CONFIG_USB_GADGET_DOWNLOAD
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#define CONFIG_G_DNL_MANUFACTURER "Rockchip"
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#define CONFIG_G_DNL_VENDOR_NUM 0x2207
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#define CONFIG_G_DNL_PRODUCT_NUM 0x310a
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/* usb host support */
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#ifdef CONFIG_CMD_USB
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#define CONFIG_USB_HOST_ETHER
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#define CONFIG_USB_ETHER_SMSC95XX
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#define CONFIG_USB_ETHER_ASIX
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#endif
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#define ENV_MEM_LAYOUT_SETTINGS \
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"scriptaddr=0x60000000\0" \
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"pxefile_addr_r=0x60100000\0" \
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"fdt_addr_r=0x61f00000\0" \
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"kernel_addr_r=0x62000000\0" \
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"ramdisk_addr_r=0x64000000\0"
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#include <config_distro_bootcmd.h>
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/* Linux fails to load the fdt if it's loaded above 256M on a Rock board,
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* so limit the fdt reallocation to that */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"fdt_high=0x6fffffff\0" \
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"initrd_high=0x6fffffff\0" \
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"partitions=" PARTS_DEFAULT \
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ENV_MEM_LAYOUT_SETTINGS \
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ROCKCHIP_DEVICE_SETTINGS \
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BOOTENV
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#endif /* CONFIG_SPL_BUILD */
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#define CONFIG_PREBOOT
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#endif
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