mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-20 17:08:52 +09:00
![Marek Vasut](/assets/img/avatar_default.png)
Enable UMS and DFU, so that the eMMC can be accessed via the USB gadget port on the board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
432 lines
9.0 KiB
C
432 lines
9.0 KiB
C
/*
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* DHCOM DH-iMX6 PDK board support
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*
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* Copyright (C) 2017 Marek Vasut <marex@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/mach-imx/sata.h>
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#include <errno.h>
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#include <fsl_esdhc.h>
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#include <fuse.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <mmc.h>
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#include <net.h>
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#include <netdev.h>
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#include <usb.h>
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#include <usb/ehci-ci.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define I2C_PAD_CTRL \
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(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
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#define EEPROM_I2C_ADDRESS 0x50
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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static struct i2c_pads_info dh6sdl_i2c_pad_info0 = {
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.scl = {
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.i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
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.gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
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.gp = IMX_GPIO_NR(3, 21)
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},
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.sda = {
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.i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
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.gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
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.gp = IMX_GPIO_NR(3, 28)
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}
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};
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static struct i2c_pads_info dh6sdl_i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
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.gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
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.gp = IMX_GPIO_NR(4, 12)
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},
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.sda = {
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.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
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.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
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.gp = IMX_GPIO_NR(4, 13)
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}
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};
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static struct i2c_pads_info dh6sdl_i2c_pad_info2 = {
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.scl = {
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.i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
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.gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
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.gp = IMX_GPIO_NR(1, 3)
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},
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.sda = {
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.i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
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.gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
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.gp = IMX_GPIO_NR(1, 6)
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}
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};
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static struct i2c_pads_info dh6dq_i2c_pad_info0 = {
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.scl = {
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.i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
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.gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
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.gp = IMX_GPIO_NR(3, 21)
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},
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.sda = {
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.i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
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.gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
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.gp = IMX_GPIO_NR(3, 28)
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}
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};
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static struct i2c_pads_info dh6dq_i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
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.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
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.gp = IMX_GPIO_NR(4, 12)
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},
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.sda = {
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.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
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.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
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.gp = IMX_GPIO_NR(4, 13)
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}
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};
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static struct i2c_pads_info dh6dq_i2c_pad_info2 = {
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.scl = {
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.i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
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.gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
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.gp = IMX_GPIO_NR(1, 3)
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},
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.sda = {
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.i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
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.gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
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.gp = IMX_GPIO_NR(1, 6)
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}
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};
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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/*
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* Do not overwrite the console
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* Use always serial for U-Boot console
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*/
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int overwrite_console(void)
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{
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return 1;
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}
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#ifdef CONFIG_FEC_MXC
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static void eth_phy_reset(void)
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{
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/* Reset PHY */
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gpio_direction_output(IMX_GPIO_NR(5, 0) , 0);
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udelay(500);
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gpio_set_value(IMX_GPIO_NR(5, 0), 1);
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/* Enable VIO */
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gpio_direction_output(IMX_GPIO_NR(1, 7) , 0);
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/*
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* KSZ9021 PHY needs at least 10 mSec after PHY reset
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* is released to stabilize
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*/
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mdelay(10);
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}
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static int setup_fec_clock(void)
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{
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struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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/* set gpr1[21] to select anatop clock */
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clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
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return enable_fec_anatop_clock(0, ENET_50MHZ);
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}
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int board_eth_init(bd_t *bis)
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{
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uint32_t base = IMX_FEC_BASE;
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struct mii_dev *bus = NULL;
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struct phy_device *phydev = NULL;
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setup_fec_clock();
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eth_phy_reset();
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bus = fec_get_miibus(base, -1);
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if (!bus)
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return -EINVAL;
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/* Scan PHY 0 */
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phydev = phy_find_by_mask(bus, 0xf, PHY_INTERFACE_MODE_RGMII);
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if (!phydev) {
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printf("Ethernet PHY not found!\n");
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return -EINVAL;
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}
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return fec_probe(bis, -1, base, bus, phydev);
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}
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#endif
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#ifdef CONFIG_FSL_ESDHC
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#define USDHC2_CD_GPIO IMX_GPIO_NR(6, 16)
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#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 8)
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static struct fsl_esdhc_cfg usdhc_cfg[3] = {
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{ USDHC2_BASE_ADDR },
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{ USDHC3_BASE_ADDR },
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{ USDHC4_BASE_ADDR },
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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switch (cfg->esdhc_base) {
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case USDHC2_BASE_ADDR:
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return gpio_get_value(USDHC2_CD_GPIO);
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case USDHC3_BASE_ADDR:
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return !gpio_get_value(USDHC3_CD_GPIO);
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case USDHC4_BASE_ADDR:
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return 1; /* eMMC/uSDHC4 is always present */
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}
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return 0;
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}
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int board_mmc_init(bd_t *bis)
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{
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int i, ret;
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/*
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* According to the board_mmc_init() the following map is done:
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* (U-Boot device node) (Physical Port)
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* mmc0 SD interface
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* mmc1 micro SD
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* mmc2 eMMC
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*/
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gpio_direction_input(USDHC2_CD_GPIO);
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gpio_direction_input(USDHC3_CD_GPIO);
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
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for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
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if (ret)
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return ret;
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}
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return 0;
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}
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#endif
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#ifdef CONFIG_USB_EHCI_MX6
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static void setup_usb(void)
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{
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/*
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* Set daisy chain for otg_pin_id on MX6Q.
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* For MX6DL, this bit is reserved.
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*/
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imx_iomux_set_gpr_register(1, 13, 1, 0);
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}
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int board_usb_phy_mode(int port)
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{
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if (port == 1)
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return USB_INIT_HOST;
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else
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return USB_INIT_DEVICE;
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}
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int board_ehci_power(int port, int on)
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{
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switch (port) {
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case 0:
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break;
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case 1:
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gpio_direction_output(IMX_GPIO_NR(3, 31), !!on);
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break;
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default:
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printf("MXC USB port %d not yet supported\n", port);
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return -EINVAL;
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}
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return 0;
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}
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#endif
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static int setup_dhcom_mac_from_fuse(void)
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{
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unsigned char enetaddr[6];
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int ret;
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ret = eth_env_get_enetaddr("ethaddr", enetaddr);
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if (ret) /* ethaddr is already set */
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return 0;
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imx_get_mac_from_fuse(0, enetaddr);
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if (is_valid_ethaddr(enetaddr)) {
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eth_env_set_enetaddr("ethaddr", enetaddr);
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return 0;
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}
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ret = i2c_set_bus_num(2);
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if (ret) {
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printf("Error switching I2C bus!\n");
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return ret;
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}
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ret = i2c_read(EEPROM_I2C_ADDRESS, 0xfa, 0x1, enetaddr, 0x6);
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if (ret) {
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printf("Error reading configuration EEPROM!\n");
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return ret;
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}
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if (is_valid_ethaddr(enetaddr))
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eth_env_set_enetaddr("ethaddr", enetaddr);
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return 0;
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}
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int board_early_init_f(void)
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{
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#ifdef CONFIG_USB_EHCI_MX6
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setup_usb();
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#endif
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return 0;
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}
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#ifdef CONFIG_MXC_SPI
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int board_spi_cs_gpio(unsigned bus, unsigned cs)
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{
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if (bus == 0 && cs == 0)
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return IMX_GPIO_NR(2, 30);
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else
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return -1;
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}
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#endif
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int board_init(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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/* Enable eim_slow clocks */
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setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
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#ifdef CONFIG_SYS_I2C_MXC
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if (is_mx6dq()) {
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setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info0);
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setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info1);
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setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info2);
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} else {
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setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info0);
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setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info1);
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setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info2);
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}
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#endif
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#ifdef CONFIG_SATA
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setup_sata();
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#endif
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setup_dhcom_mac_from_fuse();
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return 0;
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}
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#ifdef CONFIG_CMD_BMODE
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static const struct boot_mode board_boot_modes[] = {
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/* 4 bit bus width */
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{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
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{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
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/* 8 bit bus width */
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{"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
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{NULL, 0},
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};
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#endif
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#define HW_CODE_BIT_0 IMX_GPIO_NR(2, 19)
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#define HW_CODE_BIT_1 IMX_GPIO_NR(6, 6)
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#define HW_CODE_BIT_2 IMX_GPIO_NR(2, 16)
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static int board_get_hwcode(void)
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{
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int hw_code;
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gpio_direction_input(HW_CODE_BIT_0);
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gpio_direction_input(HW_CODE_BIT_1);
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gpio_direction_input(HW_CODE_BIT_2);
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/* HW 100 + HW 200 = 00b; HW 300 = 01b */
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hw_code = ((gpio_get_value(HW_CODE_BIT_2) << 2) |
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(gpio_get_value(HW_CODE_BIT_1) << 1) |
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gpio_get_value(HW_CODE_BIT_0)) + 2;
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return hw_code;
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}
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int board_late_init(void)
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{
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u32 hw_code;
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char buf[16];
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hw_code = board_get_hwcode();
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switch (get_cpu_type()) {
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case MXC_CPU_MX6SOLO:
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snprintf(buf, sizeof(buf), "imx6s-dhcom%1d", hw_code);
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break;
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case MXC_CPU_MX6DL:
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snprintf(buf, sizeof(buf), "imx6dl-dhcom%1d", hw_code);
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break;
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case MXC_CPU_MX6D:
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snprintf(buf, sizeof(buf), "imx6d-dhcom%1d", hw_code);
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break;
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case MXC_CPU_MX6Q:
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snprintf(buf, sizeof(buf), "imx6q-dhcom%1d", hw_code);
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break;
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default:
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snprintf(buf, sizeof(buf), "UNKNOWN%1d", hw_code);
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break;
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}
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env_set("dhcom", buf);
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#ifdef CONFIG_CMD_BMODE
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add_board_boot_modes(board_boot_modes);
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#endif
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: DHCOM i.MX6\n");
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return 0;
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}
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