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a0ba97e561
Use a single dtsi file for CP110 die instead of master/slave. Moving to single file will allow miltiple DTSI inclusions with re-defined CP index and name. This change will also allow support for SoCs containing more than two CP110 dies on board. Move pin control definitions from CP110 DTS to board DTS files Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
65 lines
1.4 KiB
Plaintext
65 lines
1.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016- 2021 Marvell International Ltd.
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*/
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/*
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* Device Tree file for the Armada 7040 SoC, made of an AP806 Quad and
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* one CP110.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include "armada-common.dtsi"
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#include "armada-8k.dtsi"
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#include "armada-ap806-quad.dtsi"
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/* CP110-0 Settings */
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#define CP110_NAME cp0
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#define CP110_NUM 0
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#include "armada-cp110.dtsi"
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#undef CP110_NAME
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#undef CP110_NUM
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/ {
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model = "Marvell Armada 7040";
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compatible = "marvell,armada7040", "marvell,armada-ap806-quad",
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"marvell,armada-ap806";
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};
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&cp0_pinctl {
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compatible = "marvell,mvebu-pinctrl", "marvell,7k-pinctrl";
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bank-name ="cp0-110";
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cp0_i2c0_pins: cp0-i2c-pins-0 {
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marvell,pins = < 37 38 >;
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marvell,function = <2>;
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};
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cp0_i2c1_pins: cp0-i2c-pins-1 {
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marvell,pins = < 35 36 >;
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marvell,function = <2>;
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};
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cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
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marvell,pins = < 0 1 2 3 4 5 6 7 8 9 10 11>;
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marvell,function = <3>;
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};
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cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
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marvell,pins = < 44 45 46 47 48 49 50 51
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52 53 54 55 >;
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marvell,function = <1>;
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};
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cp0_pca0_pins: cp0-pca0_pins {
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marvell,pins = <62>;
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marvell,function = <0>;
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};
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cp0_sdhci_pins: cp0-sdhi-pins-0 {
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marvell,pins = < 56 57 58 59 60 61 >;
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marvell,function = <14>;
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};
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cp0_spi0_pins: cp0-spi-pins-0 {
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marvell,pins = < 13 14 15 16 >;
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marvell,function = <3>;
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};
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};
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