mirror of
https://github.com/brain-hackers/u-boot-brain
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a0aba8a2eb
CONFIG_SYS_[DI]CACHE_OFF had been partially converted to Kconfig
parameters; only for the ARC architecture. This patch turns these two
parameters into Kconfig items everywhere else they are found.
All of the include/configs/* and defconfig changes in this patch are
for arm machines only. The Kconfig changes for arc, nds32, riscv,
and xtensa have been included since these symbols are found in code
under arch/{arc,nds32,riscv,xtensa}, however, no currently-defined
include/configs/* or defconfigs for these architectures exist which
include these symbols.
These results have been confirmed with tools/moveconfig.py.
Acked-by: Alexey Brodkin <abrodkin@snopsys.com>
Signed-off-by: Trevor Woerner <trevor@toganlabs.com>
[trini: Re-migrate for a few more boards]
Signed-off-by: Tom Rini <trini@konsulko.com>
189 lines
3.9 KiB
Plaintext
189 lines
3.9 KiB
Plaintext
menu "RISC-V architecture"
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depends on RISCV
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config SYS_ARCH
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default "riscv"
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choice
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prompt "Target select"
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optional
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config TARGET_AX25_AE350
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bool "Support ax25-ae350"
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config TARGET_QEMU_VIRT
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bool "Support QEMU Virt Board"
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config TARGET_SIFIVE_FU540
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bool "Support SiFive FU540 Board"
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endchoice
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config SYS_ICACHE_OFF
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bool "Do not enable icache"
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default n
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help
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Do not enable instruction cache in U-Boot.
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config SYS_DCACHE_OFF
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bool "Do not enable dcache"
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default n
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help
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Do not enable data cache in U-Boot.
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# board-specific options below
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source "board/AndesTech/ax25-ae350/Kconfig"
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source "board/emulation/qemu-riscv/Kconfig"
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source "board/sifive/fu540/Kconfig"
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# platform-specific options below
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source "arch/riscv/cpu/ax25/Kconfig"
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source "arch/riscv/cpu/generic/Kconfig"
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# architecture-specific options below
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choice
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prompt "Base ISA"
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default ARCH_RV32I
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config ARCH_RV32I
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bool "RV32I"
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select 32BIT
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help
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Choose this option to target the RV32I base integer instruction set.
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config ARCH_RV64I
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bool "RV64I"
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select 64BIT
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select PHYS_64BIT
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help
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Choose this option to target the RV64I base integer instruction set.
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endchoice
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choice
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prompt "Code Model"
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default CMODEL_MEDLOW
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config CMODEL_MEDLOW
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bool "medium low code model"
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help
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U-Boot and its statically defined symbols must lie within a single 2 GiB
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address range and must lie between absolute addresses -2 GiB and +2 GiB.
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config CMODEL_MEDANY
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bool "medium any code model"
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help
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U-Boot and its statically defined symbols must be within any single 2 GiB
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address range.
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endchoice
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choice
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prompt "Run Mode"
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default RISCV_MMODE
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config RISCV_MMODE
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bool "Machine"
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help
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Choose this option to build U-Boot for RISC-V M-Mode.
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config RISCV_SMODE
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bool "Supervisor"
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help
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Choose this option to build U-Boot for RISC-V S-Mode.
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endchoice
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config RISCV_ISA_C
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bool "Emit compressed instructions"
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default y
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help
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Adds "C" to the ISA subsets that the toolchain is allowed to emit
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when building U-Boot, which results in compressed instructions in the
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U-Boot binary.
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config RISCV_ISA_A
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def_bool y
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config 32BIT
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bool
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config 64BIT
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bool
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config SIFIVE_CLINT
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bool
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depends on RISCV_MMODE
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select REGMAP
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select SYSCON
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help
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The SiFive CLINT block holds memory-mapped control and status registers
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associated with software and timer interrupts.
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config ANDES_PLIC
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bool
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depends on RISCV_MMODE
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select REGMAP
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select SYSCON
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help
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The Andes PLIC block holds memory-mapped claim and pending registers
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associated with software interrupt.
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config ANDES_PLMT
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bool
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depends on RISCV_MMODE
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select REGMAP
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select SYSCON
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help
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The Andes PLMT block holds memory-mapped mtime register
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associated with timer tick.
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config RISCV_RDTIME
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bool
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default y if RISCV_SMODE
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help
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The provides the riscv_get_time() API that is implemented using the
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standard rdtime instruction. This is the case for S-mode U-Boot, and
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is useful for processors that support rdtime in M-mode too.
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config SYS_MALLOC_F_LEN
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default 0x1000
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config SMP
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bool "Symmetric Multi-Processing"
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help
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This enables support for systems with more than one CPU. If
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you say N here, U-Boot will run on single and multiprocessor
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machines, but will use only one CPU of a multiprocessor
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machine. If you say Y here, U-Boot will run on many, but not
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all, single processor machines.
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config NR_CPUS
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int "Maximum number of CPUs (2-32)"
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range 2 32
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depends on SMP
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default 8
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help
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On multiprocessor machines, U-Boot sets up a stack for each CPU.
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Stack memory is pre-allocated. U-Boot must therefore know the
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maximum number of CPUs that may be present.
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config SBI_IPI
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bool
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default y if RISCV_SMODE
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depends on SMP
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config XIP
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bool "XIP mode"
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help
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XIP (eXecute In Place) is a method for executing code directly
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from a NOR flash memory without copying the code to ram.
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Say yes here if U-Boot boots from flash directly.
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config STACK_SIZE_SHIFT
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int
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default 13
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endmenu
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