Kumar Gala a09b9b68d4 powerpc/8xxx: Refactor SRIO initialization into common code ... Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO. We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically. We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled. Introduced the following standard defines for board config.h: CONFIG_SYS_SRIO - Chip has SRIO or not CONFIG_SRIO1 - Board has SRIO 1 port available CONFIG_SRIO2 - Board has SRIO 2 port available (where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup) [ These mimic what we have for PCI and PCIe controllers ] Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>		2011-01-14 01:32:21 -06:00
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config.mk	Makefile: move all Power Architecture boards into boards.cfg	2010-10-18 22:12:04 +02:00
corenet_ds.c	powerpc/8xxx: Refactor SRIO initialization into common code	2011-01-14 01:32:21 -06:00
ddr.c	Adding fixed sdram setting for cornet_ds board	2010-10-20 02:38:39 -05:00
law.c	powerpc/p4080: Add support for the P4080DS board	2010-08-01 11:18:40 -05:00
Makefile	Switch from archive libraries to partial linking	2010-11-17 21:02:18 +01:00
p4080ds_ddr.c	Adding fixed sdram setting for cornet_ds board	2010-10-20 02:38:39 -05:00
pci.c	powerpc/85xx: Rework corenet_ds pci_init_board to use common FSL PCIe code	2011-01-14 01:32:21 -06:00
tlb.c	powerpc/p4080: Add support for the P4080DS board	2010-08-01 11:18:40 -05:00