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https://github.com/brain-hackers/u-boot-brain
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![Akshay Saraswat](/assets/img/avatar_default.png)
This patch includes following changes : * Adds gpio pin numbering support for EXYNOS SOCs. To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them. * Rename GPIO definitions from GPIO_... to S5P_GPIO_... These changes were done to enable cmd_gpio for EXYNOS and cmd_gpio has GPIO_INPUT same as s5p_gpio driver and hence getting a error during compilation. * Adds support for name to gpio conversion in s5p_gpio to enable gpio command EXYNOS SoCs. Function has been added to asm/gpio.h to decode the input gpio name to gpio number. Example: SMDK5420 # gpio set gpa00 Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
320 lines
6.9 KiB
C
320 lines
6.9 KiB
C
/*
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* (C) Copyright 2009 Samsung Electronics
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* Minkyu Kang <mk7.kang@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/gpio.h>
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#define S5P_GPIO_GET_PIN(x) (x % GPIO_PER_BANK)
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#define CON_MASK(x) (0xf << ((x) << 2))
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#define CON_SFR(x, v) ((v) << ((x) << 2))
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#define DAT_MASK(x) (0x1 << (x))
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#define DAT_SET(x) (0x1 << (x))
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#define PULL_MASK(x) (0x3 << ((x) << 1))
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#define PULL_MODE(x, v) ((v) << ((x) << 1))
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#define DRV_MASK(x) (0x3 << ((x) << 1))
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#define DRV_SET(x, m) ((m) << ((x) << 1))
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#define RATE_MASK(x) (0x1 << (x + 16))
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#define RATE_SET(x) (0x1 << (x + 16))
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#define name_to_gpio(n) s5p_name_to_gpio(n)
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static inline int s5p_name_to_gpio(const char *name)
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{
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unsigned num, irregular_set_number, irregular_bank_base;
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const struct gpio_name_num_table *tabp;
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char this_bank, bank_name, irregular_bank_name;
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char *endp;
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/*
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* The gpio name starts with either 'g' or 'gp' followed by the bank
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* name character. Skip one or two characters depending on the prefix.
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*/
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if (name[0] == 'g' && name[1] == 'p')
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name += 2;
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else if (name[0] == 'g')
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name++;
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else
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return -1; /* Name must start with 'g' */
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bank_name = *name++;
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if (!*name)
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return -1; /* At least one digit is required/expected. */
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/*
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* On both exynos5 and exynos5420 architectures there is a bank of
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* GPIOs which does not fall into the regular address pattern. Those
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* banks are c4 on Exynos5 and y7 on Exynos5420. The rest of the below
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* assignments help to handle these irregularities.
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*/
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#if defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5)
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if (cpu_is_exynos5()) {
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if (proid_is_exynos5420()) {
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tabp = exynos5420_gpio_table;
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irregular_bank_name = 'y';
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irregular_set_number = '7';
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irregular_bank_base = EXYNOS5420_GPIO_Y70;
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} else {
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tabp = exynos5_gpio_table;
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irregular_bank_name = 'c';
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irregular_set_number = '4';
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irregular_bank_base = EXYNOS5_GPIO_C40;
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}
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} else {
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if (proid_is_exynos4412())
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tabp = exynos4x12_gpio_table;
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else
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tabp = exynos4_gpio_table;
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irregular_bank_name = 0;
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irregular_set_number = 0;
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irregular_bank_base = 0;
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}
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#else
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if (cpu_is_s5pc110())
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tabp = s5pc110_gpio_table;
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else
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tabp = s5pc100_gpio_table;
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irregular_bank_name = 0;
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irregular_set_number = 0;
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irregular_bank_base = 0;
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#endif
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this_bank = tabp->bank;
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do {
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if (bank_name == this_bank) {
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unsigned pin_index; /* pin number within the bank */
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if ((bank_name == irregular_bank_name) &&
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(name[0] == irregular_set_number)) {
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pin_index = name[1] - '0';
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/* Irregular sets have 8 pins. */
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if (pin_index >= GPIO_PER_BANK)
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return -1;
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num = irregular_bank_base + pin_index;
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} else {
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pin_index = simple_strtoul(name, &endp, 8);
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pin_index -= tabp->bank_offset;
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/*
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* Sanity check: bunk 'z' has no set number,
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* for all other banks there must be exactly
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* two octal digits, and the resulting number
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* should not exceed the number of pins in the
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* bank.
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*/
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if (((bank_name != 'z') && !name[1]) ||
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*endp ||
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(pin_index >= tabp->bank_size))
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return -1;
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num = tabp->base + pin_index;
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}
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return num;
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}
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this_bank = (++tabp)->bank;
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} while (this_bank);
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return -1;
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}
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static void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
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{
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unsigned int value;
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value = readl(&bank->con);
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value &= ~CON_MASK(gpio);
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value |= CON_SFR(gpio, cfg);
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writel(value, &bank->con);
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}
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static void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en)
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{
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unsigned int value;
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value = readl(&bank->dat);
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value &= ~DAT_MASK(gpio);
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if (en)
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value |= DAT_SET(gpio);
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writel(value, &bank->dat);
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}
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static void s5p_gpio_direction_output(struct s5p_gpio_bank *bank,
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int gpio, int en)
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{
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s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_OUTPUT);
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s5p_gpio_set_value(bank, gpio, en);
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}
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static void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio)
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{
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s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_INPUT);
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}
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static unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio)
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{
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unsigned int value;
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value = readl(&bank->dat);
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return !!(value & DAT_MASK(gpio));
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}
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static void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode)
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{
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unsigned int value;
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value = readl(&bank->pull);
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value &= ~PULL_MASK(gpio);
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switch (mode) {
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case S5P_GPIO_PULL_DOWN:
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case S5P_GPIO_PULL_UP:
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value |= PULL_MODE(gpio, mode);
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break;
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default:
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break;
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}
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writel(value, &bank->pull);
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}
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static void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode)
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{
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unsigned int value;
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value = readl(&bank->drv);
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value &= ~DRV_MASK(gpio);
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switch (mode) {
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case S5P_GPIO_DRV_1X:
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case S5P_GPIO_DRV_2X:
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case S5P_GPIO_DRV_3X:
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case S5P_GPIO_DRV_4X:
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value |= DRV_SET(gpio, mode);
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break;
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default:
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return;
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}
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writel(value, &bank->drv);
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}
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static void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
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{
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unsigned int value;
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value = readl(&bank->drv);
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value &= ~RATE_MASK(gpio);
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switch (mode) {
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case S5P_GPIO_DRV_FAST:
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case S5P_GPIO_DRV_SLOW:
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value |= RATE_SET(gpio);
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break;
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default:
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return;
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}
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writel(value, &bank->drv);
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}
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struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)
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{
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const struct gpio_info *data;
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unsigned int upto;
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int i, count;
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data = get_gpio_data();
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count = get_bank_num();
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upto = 0;
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for (i = 0; i < count; i++) {
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debug("i=%d, upto=%d\n", i, upto);
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if (gpio < data->max_gpio) {
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struct s5p_gpio_bank *bank;
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bank = (struct s5p_gpio_bank *)data->reg_addr;
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bank += (gpio - upto) / GPIO_PER_BANK;
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debug("gpio=%d, bank=%p\n", gpio, bank);
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return bank;
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}
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upto = data->max_gpio;
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data++;
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}
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return NULL;
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}
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int s5p_gpio_get_pin(unsigned gpio)
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{
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return S5P_GPIO_GET_PIN(gpio);
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}
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/* Common GPIO API */
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int gpio_request(unsigned gpio, const char *label)
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{
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return 0;
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}
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int gpio_free(unsigned gpio)
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{
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return 0;
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}
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int gpio_direction_input(unsigned gpio)
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{
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s5p_gpio_direction_input(s5p_gpio_get_bank(gpio),
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s5p_gpio_get_pin(gpio));
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return 0;
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}
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int gpio_direction_output(unsigned gpio, int value)
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{
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s5p_gpio_direction_output(s5p_gpio_get_bank(gpio),
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s5p_gpio_get_pin(gpio), value);
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return 0;
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}
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int gpio_get_value(unsigned gpio)
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{
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return (int) s5p_gpio_get_value(s5p_gpio_get_bank(gpio),
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s5p_gpio_get_pin(gpio));
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}
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int gpio_set_value(unsigned gpio, int value)
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{
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s5p_gpio_set_value(s5p_gpio_get_bank(gpio),
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s5p_gpio_get_pin(gpio), value);
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return 0;
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}
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void gpio_set_pull(int gpio, int mode)
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{
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s5p_gpio_set_pull(s5p_gpio_get_bank(gpio),
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s5p_gpio_get_pin(gpio), mode);
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}
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void gpio_set_drv(int gpio, int mode)
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{
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s5p_gpio_set_drv(s5p_gpio_get_bank(gpio),
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s5p_gpio_get_pin(gpio), mode);
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}
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void gpio_cfg_pin(int gpio, int cfg)
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{
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s5p_gpio_cfg_pin(s5p_gpio_get_bank(gpio),
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s5p_gpio_get_pin(gpio), cfg);
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}
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void gpio_set_rate(int gpio, int mode)
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{
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s5p_gpio_set_rate(s5p_gpio_get_bank(gpio),
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s5p_gpio_get_pin(gpio), mode);
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}
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