Pragnesh Patel 5ce50206ed riscv: sifive: fu540: enable all cache ways from U-Boot proper ... Add L2 cache node to enable all cache ways from U-Boot proper. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>		2020-07-03 15:09:06 +08:00
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cache.h	riscv: sifive: fu540: enable all cache ways from U-Boot proper	2020-07-03 15:09:06 +08:00
clk.h	riscv: cpu: fu540: Add support for cpu fu540	2020-06-04 09:44:09 +08:00
gpio.h	riscv: cpu: fu540: Add support for cpu fu540	2020-06-04 09:44:09 +08:00
spl.h	riscv: sifive: fu540: add SPL configuration	2020-06-04 09:44:09 +08:00