mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-27 20:38:52 +09:00
![Jagan Teki](/assets/img/avatar_default.png)
Sync the hifive-unleashed-a00 dts from Linux with below commit details: commit <2993c9b04e616df0848b655d7202a707a70fc876> ("riscv: dts: HiFive Unleashed: add default chosen/stdout-path") Idea is to periodically sync the dts from Linux instead of tweaking internal changes one after another, so better not add any intermediate changes in between. This would help to maintain the dts files easy and meaningful since we are reusing device tree files from Linux. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
252 lines
6.3 KiB
Plaintext
252 lines
6.3 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
|
/* Copyright (c) 2018-2019 SiFive, Inc */
|
|
|
|
/dts-v1/;
|
|
|
|
#include <dt-bindings/clock/sifive-fu540-prci.h>
|
|
|
|
/ {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
compatible = "sifive,fu540-c000", "sifive,fu540";
|
|
|
|
aliases {
|
|
serial0 = &uart0;
|
|
serial1 = &uart1;
|
|
ethernet0 = ð0;
|
|
};
|
|
|
|
chosen {
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
cpu0: cpu@0 {
|
|
compatible = "sifive,e51", "sifive,rocket0", "riscv";
|
|
device_type = "cpu";
|
|
i-cache-block-size = <64>;
|
|
i-cache-sets = <128>;
|
|
i-cache-size = <16384>;
|
|
reg = <0>;
|
|
riscv,isa = "rv64imac";
|
|
status = "disabled";
|
|
cpu0_intc: interrupt-controller {
|
|
#interrupt-cells = <1>;
|
|
compatible = "riscv,cpu-intc";
|
|
interrupt-controller;
|
|
};
|
|
};
|
|
cpu1: cpu@1 {
|
|
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
|
|
d-cache-block-size = <64>;
|
|
d-cache-sets = <64>;
|
|
d-cache-size = <32768>;
|
|
d-tlb-sets = <1>;
|
|
d-tlb-size = <32>;
|
|
device_type = "cpu";
|
|
i-cache-block-size = <64>;
|
|
i-cache-sets = <64>;
|
|
i-cache-size = <32768>;
|
|
i-tlb-sets = <1>;
|
|
i-tlb-size = <32>;
|
|
mmu-type = "riscv,sv39";
|
|
reg = <1>;
|
|
riscv,isa = "rv64imafdc";
|
|
tlb-split;
|
|
cpu1_intc: interrupt-controller {
|
|
#interrupt-cells = <1>;
|
|
compatible = "riscv,cpu-intc";
|
|
interrupt-controller;
|
|
};
|
|
};
|
|
cpu2: cpu@2 {
|
|
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
|
|
d-cache-block-size = <64>;
|
|
d-cache-sets = <64>;
|
|
d-cache-size = <32768>;
|
|
d-tlb-sets = <1>;
|
|
d-tlb-size = <32>;
|
|
device_type = "cpu";
|
|
i-cache-block-size = <64>;
|
|
i-cache-sets = <64>;
|
|
i-cache-size = <32768>;
|
|
i-tlb-sets = <1>;
|
|
i-tlb-size = <32>;
|
|
mmu-type = "riscv,sv39";
|
|
reg = <2>;
|
|
riscv,isa = "rv64imafdc";
|
|
tlb-split;
|
|
cpu2_intc: interrupt-controller {
|
|
#interrupt-cells = <1>;
|
|
compatible = "riscv,cpu-intc";
|
|
interrupt-controller;
|
|
};
|
|
};
|
|
cpu3: cpu@3 {
|
|
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
|
|
d-cache-block-size = <64>;
|
|
d-cache-sets = <64>;
|
|
d-cache-size = <32768>;
|
|
d-tlb-sets = <1>;
|
|
d-tlb-size = <32>;
|
|
device_type = "cpu";
|
|
i-cache-block-size = <64>;
|
|
i-cache-sets = <64>;
|
|
i-cache-size = <32768>;
|
|
i-tlb-sets = <1>;
|
|
i-tlb-size = <32>;
|
|
mmu-type = "riscv,sv39";
|
|
reg = <3>;
|
|
riscv,isa = "rv64imafdc";
|
|
tlb-split;
|
|
cpu3_intc: interrupt-controller {
|
|
#interrupt-cells = <1>;
|
|
compatible = "riscv,cpu-intc";
|
|
interrupt-controller;
|
|
};
|
|
};
|
|
cpu4: cpu@4 {
|
|
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
|
|
d-cache-block-size = <64>;
|
|
d-cache-sets = <64>;
|
|
d-cache-size = <32768>;
|
|
d-tlb-sets = <1>;
|
|
d-tlb-size = <32>;
|
|
device_type = "cpu";
|
|
i-cache-block-size = <64>;
|
|
i-cache-sets = <64>;
|
|
i-cache-size = <32768>;
|
|
i-tlb-sets = <1>;
|
|
i-tlb-size = <32>;
|
|
mmu-type = "riscv,sv39";
|
|
reg = <4>;
|
|
riscv,isa = "rv64imafdc";
|
|
tlb-split;
|
|
cpu4_intc: interrupt-controller {
|
|
#interrupt-cells = <1>;
|
|
compatible = "riscv,cpu-intc";
|
|
interrupt-controller;
|
|
};
|
|
};
|
|
};
|
|
soc {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
|
|
ranges;
|
|
plic0: interrupt-controller@c000000 {
|
|
#interrupt-cells = <1>;
|
|
compatible = "sifive,plic-1.0.0";
|
|
reg = <0x0 0xc000000 0x0 0x4000000>;
|
|
riscv,ndev = <53>;
|
|
interrupt-controller;
|
|
interrupts-extended = <
|
|
&cpu0_intc 0xffffffff
|
|
&cpu1_intc 0xffffffff &cpu1_intc 9
|
|
&cpu2_intc 0xffffffff &cpu2_intc 9
|
|
&cpu3_intc 0xffffffff &cpu3_intc 9
|
|
&cpu4_intc 0xffffffff &cpu4_intc 9>;
|
|
};
|
|
prci: clock-controller@10000000 {
|
|
compatible = "sifive,fu540-c000-prci";
|
|
reg = <0x0 0x10000000 0x0 0x1000>;
|
|
clocks = <&hfclk>, <&rtcclk>;
|
|
#clock-cells = <1>;
|
|
};
|
|
uart0: serial@10010000 {
|
|
compatible = "sifive,fu540-c000-uart", "sifive,uart0";
|
|
reg = <0x0 0x10010000 0x0 0x1000>;
|
|
interrupt-parent = <&plic0>;
|
|
interrupts = <4>;
|
|
clocks = <&prci PRCI_CLK_TLCLK>;
|
|
status = "disabled";
|
|
};
|
|
uart1: serial@10011000 {
|
|
compatible = "sifive,fu540-c000-uart", "sifive,uart0";
|
|
reg = <0x0 0x10011000 0x0 0x1000>;
|
|
interrupt-parent = <&plic0>;
|
|
interrupts = <5>;
|
|
clocks = <&prci PRCI_CLK_TLCLK>;
|
|
status = "disabled";
|
|
};
|
|
i2c0: i2c@10030000 {
|
|
compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
|
|
reg = <0x0 0x10030000 0x0 0x1000>;
|
|
interrupt-parent = <&plic0>;
|
|
interrupts = <50>;
|
|
clocks = <&prci PRCI_CLK_TLCLK>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
qspi0: spi@10040000 {
|
|
compatible = "sifive,fu540-c000-spi", "sifive,spi0";
|
|
reg = <0x0 0x10040000 0x0 0x1000
|
|
0x0 0x20000000 0x0 0x10000000>;
|
|
interrupt-parent = <&plic0>;
|
|
interrupts = <51>;
|
|
clocks = <&prci PRCI_CLK_TLCLK>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
qspi1: spi@10041000 {
|
|
compatible = "sifive,fu540-c000-spi", "sifive,spi0";
|
|
reg = <0x0 0x10041000 0x0 0x1000
|
|
0x0 0x30000000 0x0 0x10000000>;
|
|
interrupt-parent = <&plic0>;
|
|
interrupts = <52>;
|
|
clocks = <&prci PRCI_CLK_TLCLK>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
qspi2: spi@10050000 {
|
|
compatible = "sifive,fu540-c000-spi", "sifive,spi0";
|
|
reg = <0x0 0x10050000 0x0 0x1000>;
|
|
interrupt-parent = <&plic0>;
|
|
interrupts = <6>;
|
|
clocks = <&prci PRCI_CLK_TLCLK>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
eth0: ethernet@10090000 {
|
|
compatible = "sifive,fu540-c000-gem";
|
|
interrupt-parent = <&plic0>;
|
|
interrupts = <53>;
|
|
reg = <0x0 0x10090000 0x0 0x2000
|
|
0x0 0x100a0000 0x0 0x1000>;
|
|
local-mac-address = [00 00 00 00 00 00];
|
|
clock-names = "pclk", "hclk";
|
|
clocks = <&prci PRCI_CLK_GEMGXLPLL>,
|
|
<&prci PRCI_CLK_GEMGXLPLL>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
pwm0: pwm@10020000 {
|
|
compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
|
|
reg = <0x0 0x10020000 0x0 0x1000>;
|
|
interrupt-parent = <&plic0>;
|
|
interrupts = <42 43 44 45>;
|
|
clocks = <&prci PRCI_CLK_TLCLK>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
pwm1: pwm@10021000 {
|
|
compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
|
|
reg = <0x0 0x10021000 0x0 0x1000>;
|
|
interrupt-parent = <&plic0>;
|
|
interrupts = <46 47 48 49>;
|
|
clocks = <&prci PRCI_CLK_TLCLK>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
};
|
|
};
|