mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 22:26:16 +09:00
a04eba99f5
On Seaboard the UART and SPI interfere with each other. This causes the UART to receive spurious zero bytes after SPI transactions and also means that SPI can corrupt a few output characters when it starts up if they are still in the UART buffer. This updates the board to use the SPI/UART switch to avoid the problem. For now this feature is turned off since it needs changes to the NS16550 UART to operate. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
106 lines
2.9 KiB
C
106 lines
2.9 KiB
C
/*
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* (C) Copyright 2010,2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/tegra2.h>
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#include <asm/arch/pinmux.h>
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#include <asm/gpio.h>
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#ifdef CONFIG_TEGRA2_MMC
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#include <mmc.h>
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#endif
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#include "../common/board.h"
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/* TODO: Remove this code when the SPI switch is working */
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#ifndef CONFIG_SPI_UART_SWITCH
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/*
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* Routine: gpio_config_uart_seaboard
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* Description: Force GPIO_PI3 low on Seaboard so UART4 works.
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*/
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static void gpio_config_uart_seaboard(void)
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{
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/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
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gpio_request(GPIO_PI3, NULL);
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gpio_direction_output(GPIO_PI3, 0);
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}
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void gpio_config_uart(void)
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{
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if (machine_is_ventana())
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return;
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gpio_config_uart_seaboard();
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}
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#endif
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#ifdef CONFIG_TEGRA2_MMC
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/*
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* Routine: pin_mux_mmc
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* Description: setup the pin muxes/tristate values for the SDMMC(s)
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*/
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static void pin_mux_mmc(void)
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{
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/* SDMMC4: config 3, x8 on 2nd set of pins */
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pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
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pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
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pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
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pinmux_tristate_disable(PINGRP_ATB);
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pinmux_tristate_disable(PINGRP_GMA);
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pinmux_tristate_disable(PINGRP_GME);
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/* SDMMC3: SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */
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pinmux_set_func(PINGRP_SDB, PMUX_FUNC_SDIO3);
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pinmux_set_func(PINGRP_SDC, PMUX_FUNC_SDIO3);
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pinmux_set_func(PINGRP_SDD, PMUX_FUNC_SDIO3);
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pinmux_tristate_disable(PINGRP_SDC);
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pinmux_tristate_disable(PINGRP_SDD);
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pinmux_tristate_disable(PINGRP_SDB);
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/* For power GPIO PI6 */
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pinmux_tristate_disable(PINGRP_ATA);
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/* For CD GPIO PI5 */
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pinmux_tristate_disable(PINGRP_ATC);
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}
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/* this is a weak define that we are overriding */
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int board_mmc_init(bd_t *bd)
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{
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debug("board_mmc_init called\n");
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/* Enable muxes, etc. for SDMMC controllers */
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pin_mux_mmc();
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debug("board_mmc_init: init eMMC\n");
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/* init dev 0, eMMC chip, with 4-bit bus */
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/* The board has an 8-bit bus, but 8-bit doesn't work yet */
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tegra2_mmc_init(0, 4, -1, -1);
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debug("board_mmc_init: init SD slot\n");
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/* init dev 1, SD slot, with 4-bit bus */
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tegra2_mmc_init(1, 4, GPIO_PI6, GPIO_PI5);
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return 0;
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}
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#endif
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