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https://github.com/brain-hackers/u-boot-brain
synced 2024-09-04 11:53:21 +09:00
![Aneesh Bansal](/assets/img/avatar_default.png)
The SEC driver code has been cleaned up to work for 64 bit physical addresses and systems where endianess of SEC block is different from the Core. Changes: 1. Descriptor created on Core is modified as per SEC block endianness before the job is submitted. 2. The read/write of physical addresses to Job Rings will be depend on endianness of SEC block as 32 bit low and high part of the 64 bit address will vary. 3. The 32 bit low and high part of the 64 bit address in descriptor will vary depending on endianness of SEC. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
559 lines
14 KiB
C
559 lines
14 KiB
C
/*
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* Copyright 2008-2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Based on CAAM driver in drivers/crypto/caam in Linux
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*/
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#include <common.h>
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#include <malloc.h>
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#include "fsl_sec.h"
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#include "jr.h"
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#include "jobdesc.h"
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#include "desc_constr.h"
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#define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
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#define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
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struct jobring jr;
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static inline void start_jr0(void)
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{
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ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
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u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
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u32 scfgr = sec_in32(&sec->scfgr);
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if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
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/* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
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* VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SEC_SCFGR_VIRT_EN = 1
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*/
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if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
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(!(ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) &&
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(scfgr & SEC_SCFGR_VIRT_EN)))
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sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
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} else {
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/* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
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if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
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sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
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}
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}
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static inline void jr_reset_liodn(void)
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{
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ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
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sec_out32(&sec->jrliodnr[0].ls, 0);
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}
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static inline void jr_disable_irq(void)
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{
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struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
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uint32_t jrcfg = sec_in32(®s->jrcfg1);
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jrcfg = jrcfg | JR_INTMASK;
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sec_out32(®s->jrcfg1, jrcfg);
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}
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static void jr_initregs(void)
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{
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struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
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phys_addr_t ip_base = virt_to_phys((void *)jr.input_ring);
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phys_addr_t op_base = virt_to_phys((void *)jr.output_ring);
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#ifdef CONFIG_PHYS_64BIT
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sec_out32(®s->irba_h, ip_base >> 32);
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#else
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sec_out32(®s->irba_h, 0x0);
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#endif
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sec_out32(®s->irba_l, (uint32_t)ip_base);
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#ifdef CONFIG_PHYS_64BIT
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sec_out32(®s->orba_h, op_base >> 32);
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#else
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sec_out32(®s->orba_h, 0x0);
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#endif
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sec_out32(®s->orba_l, (uint32_t)op_base);
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sec_out32(®s->ors, JR_SIZE);
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sec_out32(®s->irs, JR_SIZE);
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if (!jr.irq)
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jr_disable_irq();
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}
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static int jr_init(void)
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{
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memset(&jr, 0, sizeof(struct jobring));
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jr.jq_id = DEFAULT_JR_ID;
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jr.irq = DEFAULT_IRQ;
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#ifdef CONFIG_FSL_CORENET
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jr.liodn = DEFAULT_JR_LIODN;
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#endif
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jr.size = JR_SIZE;
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jr.input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
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JR_SIZE * sizeof(dma_addr_t));
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if (!jr.input_ring)
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return -1;
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jr.output_ring =
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(struct op_ring *)memalign(ARCH_DMA_MINALIGN,
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JR_SIZE * sizeof(struct op_ring));
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if (!jr.output_ring)
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return -1;
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memset(jr.input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
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memset(jr.output_ring, 0, JR_SIZE * sizeof(struct op_ring));
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start_jr0();
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jr_initregs();
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return 0;
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}
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static int jr_sw_cleanup(void)
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{
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jr.head = 0;
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jr.tail = 0;
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jr.read_idx = 0;
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jr.write_idx = 0;
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memset(jr.info, 0, sizeof(jr.info));
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memset(jr.input_ring, 0, jr.size * sizeof(dma_addr_t));
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memset(jr.output_ring, 0, jr.size * sizeof(struct op_ring));
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return 0;
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}
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static int jr_hw_reset(void)
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{
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struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
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uint32_t timeout = 100000;
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uint32_t jrint, jrcr;
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sec_out32(®s->jrcr, JRCR_RESET);
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do {
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jrint = sec_in32(®s->jrint);
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} while (((jrint & JRINT_ERR_HALT_MASK) ==
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JRINT_ERR_HALT_INPROGRESS) && --timeout);
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jrint = sec_in32(®s->jrint);
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if (((jrint & JRINT_ERR_HALT_MASK) !=
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JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
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return -1;
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timeout = 100000;
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sec_out32(®s->jrcr, JRCR_RESET);
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do {
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jrcr = sec_in32(®s->jrcr);
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} while ((jrcr & JRCR_RESET) && --timeout);
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if (timeout == 0)
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return -1;
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return 0;
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}
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/* -1 --- error, can't enqueue -- no space available */
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static int jr_enqueue(uint32_t *desc_addr,
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void (*callback)(uint32_t status, void *arg),
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void *arg)
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{
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struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
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int head = jr.head;
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uint32_t desc_word;
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int length = desc_len(desc_addr);
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int i;
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#ifdef CONFIG_PHYS_64BIT
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uint32_t *addr_hi, *addr_lo;
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#endif
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/* The descriptor must be submitted to SEC block as per endianness
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* of the SEC Block.
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* So, if the endianness of Core and SEC block is different, each word
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* of the descriptor will be byte-swapped.
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*/
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for (i = 0; i < length; i++) {
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desc_word = desc_addr[i];
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sec_out32((uint32_t *)&desc_addr[i], desc_word);
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}
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phys_addr_t desc_phys_addr = virt_to_phys(desc_addr);
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if (sec_in32(®s->irsa) == 0 ||
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CIRC_SPACE(jr.head, jr.tail, jr.size) <= 0)
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return -1;
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jr.info[head].desc_phys_addr = desc_phys_addr;
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jr.info[head].callback = (void *)callback;
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jr.info[head].arg = arg;
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jr.info[head].op_done = 0;
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unsigned long start = (unsigned long)&jr.info[head] &
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~(ARCH_DMA_MINALIGN - 1);
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unsigned long end = ALIGN(start + sizeof(struct jr_info),
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ARCH_DMA_MINALIGN);
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flush_dcache_range(start, end);
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#ifdef CONFIG_PHYS_64BIT
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/* Write the 64 bit Descriptor address on Input Ring.
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* The 32 bit hign and low part of the address will
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* depend on endianness of SEC block.
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*/
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#ifdef CONFIG_SYS_FSL_SEC_LE
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addr_lo = (uint32_t *)(&jr.input_ring[head]);
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addr_hi = (uint32_t *)(&jr.input_ring[head]) + 1;
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#elif defined(CONFIG_SYS_FSL_SEC_BE)
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addr_hi = (uint32_t *)(&jr.input_ring[head]);
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addr_lo = (uint32_t *)(&jr.input_ring[head]) + 1;
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#endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
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sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32));
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sec_out32(addr_lo, (uint32_t)(desc_phys_addr));
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#else
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/* Write the 32 bit Descriptor address on Input Ring. */
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sec_out32(&jr.input_ring[head], desc_phys_addr);
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#endif /* ifdef CONFIG_PHYS_64BIT */
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start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
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end = ALIGN(start + sizeof(phys_addr_t), ARCH_DMA_MINALIGN);
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flush_dcache_range(start, end);
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jr.head = (head + 1) & (jr.size - 1);
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sec_out32(®s->irja, 1);
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return 0;
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}
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static int jr_dequeue(void)
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{
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struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
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int head = jr.head;
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int tail = jr.tail;
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int idx, i, found;
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void (*callback)(uint32_t status, void *arg);
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void *arg = NULL;
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#ifdef CONFIG_PHYS_64BIT
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uint32_t *addr_hi, *addr_lo;
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#else
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uint32_t *addr;
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#endif
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while (sec_in32(®s->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) {
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unsigned long start = (unsigned long)jr.output_ring &
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~(ARCH_DMA_MINALIGN - 1);
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unsigned long end = ALIGN(start +
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sizeof(struct op_ring)*JR_SIZE,
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ARCH_DMA_MINALIGN);
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invalidate_dcache_range(start, end);
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found = 0;
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phys_addr_t op_desc;
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#ifdef CONFIG_PHYS_64BIT
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/* Read the 64 bit Descriptor address from Output Ring.
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* The 32 bit hign and low part of the address will
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* depend on endianness of SEC block.
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*/
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#ifdef CONFIG_SYS_FSL_SEC_LE
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addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc);
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addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1;
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#elif defined(CONFIG_SYS_FSL_SEC_BE)
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addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc);
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addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1;
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#endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
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op_desc = ((u64)sec_in32(addr_hi) << 32) |
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((u64)sec_in32(addr_lo));
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#else
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/* Read the 32 bit Descriptor address from Output Ring. */
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addr = (uint32_t *)&jr.output_ring[jr.tail].desc;
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op_desc = sec_in32(addr);
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#endif /* ifdef CONFIG_PHYS_64BIT */
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uint32_t status = sec_in32(&jr.output_ring[jr.tail].status);
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for (i = 0; CIRC_CNT(head, tail + i, jr.size) >= 1; i++) {
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idx = (tail + i) & (jr.size - 1);
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if (op_desc == jr.info[idx].desc_phys_addr) {
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found = 1;
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break;
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}
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}
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/* Error condition if match not found */
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if (!found)
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return -1;
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jr.info[idx].op_done = 1;
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callback = (void *)jr.info[idx].callback;
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arg = jr.info[idx].arg;
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/* When the job on tail idx gets done, increment
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* tail till the point where job completed out of oredr has
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* been taken into account
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*/
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if (idx == tail)
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do {
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tail = (tail + 1) & (jr.size - 1);
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} while (jr.info[tail].op_done);
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jr.tail = tail;
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jr.read_idx = (jr.read_idx + 1) & (jr.size - 1);
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sec_out32(®s->orjr, 1);
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jr.info[idx].op_done = 0;
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callback(status, arg);
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}
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return 0;
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}
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static void desc_done(uint32_t status, void *arg)
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{
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struct result *x = arg;
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x->status = status;
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caam_jr_strstatus(status);
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x->done = 1;
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}
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int run_descriptor_jr(uint32_t *desc)
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{
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unsigned long long timeval = get_ticks();
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unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
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struct result op;
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int ret = 0;
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memset(&op, 0, sizeof(op));
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ret = jr_enqueue(desc, desc_done, &op);
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if (ret) {
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debug("Error in SEC enq\n");
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ret = JQ_ENQ_ERR;
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goto out;
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}
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timeval = get_ticks();
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timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
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while (op.done != 1) {
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ret = jr_dequeue();
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if (ret) {
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debug("Error in SEC deq\n");
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ret = JQ_DEQ_ERR;
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goto out;
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}
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if ((get_ticks() - timeval) > timeout) {
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debug("SEC Dequeue timed out\n");
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ret = JQ_DEQ_TO_ERR;
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goto out;
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}
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}
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if (!op.status) {
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debug("Error %x\n", op.status);
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ret = op.status;
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}
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out:
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return ret;
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}
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int jr_reset(void)
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{
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if (jr_hw_reset() < 0)
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return -1;
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/* Clean up the jobring structure maintained by software */
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jr_sw_cleanup();
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return 0;
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}
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int sec_reset(void)
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{
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ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
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uint32_t mcfgr = sec_in32(&sec->mcfgr);
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uint32_t timeout = 100000;
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mcfgr |= MCFGR_SWRST;
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sec_out32(&sec->mcfgr, mcfgr);
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mcfgr |= MCFGR_DMA_RST;
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sec_out32(&sec->mcfgr, mcfgr);
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do {
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mcfgr = sec_in32(&sec->mcfgr);
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} while ((mcfgr & MCFGR_DMA_RST) == MCFGR_DMA_RST && --timeout);
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if (timeout == 0)
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return -1;
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timeout = 100000;
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do {
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mcfgr = sec_in32(&sec->mcfgr);
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} while ((mcfgr & MCFGR_SWRST) == MCFGR_SWRST && --timeout);
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if (timeout == 0)
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return -1;
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return 0;
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}
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static int instantiate_rng(void)
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{
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struct result op;
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u32 *desc;
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u32 rdsta_val;
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int ret = 0;
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ccsr_sec_t __iomem *sec =
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(ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
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struct rng4tst __iomem *rng =
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(struct rng4tst __iomem *)&sec->rng;
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memset(&op, 0, sizeof(struct result));
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desc = memalign(ARCH_DMA_MINALIGN, sizeof(uint32_t) * 6);
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if (!desc) {
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printf("cannot allocate RNG init descriptor memory\n");
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return -1;
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}
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inline_cnstr_jobdesc_rng_instantiation(desc);
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int size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN);
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flush_dcache_range((unsigned long)desc,
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(unsigned long)desc + size);
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ret = run_descriptor_jr(desc);
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if (ret)
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printf("RNG: Instantiation failed with error %x\n", ret);
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rdsta_val = sec_in32(&rng->rdsta);
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if (op.status || !(rdsta_val & RNG_STATE0_HANDLE_INSTANTIATED))
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return -1;
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return ret;
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}
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static u8 get_rng_vid(void)
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{
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ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
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u32 cha_vid = sec_in32(&sec->chavid_ls);
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return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT;
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}
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/*
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* By default, the TRNG runs for 200 clocks per sample;
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* 1200 clocks per sample generates better entropy.
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*/
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static void kick_trng(int ent_delay)
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{
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ccsr_sec_t __iomem *sec =
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(ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
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struct rng4tst __iomem *rng =
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(struct rng4tst __iomem *)&sec->rng;
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u32 val;
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/* put RNG4 into program mode */
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sec_setbits32(&rng->rtmctl, RTMCTL_PRGM);
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/* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
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* length (in system clocks) of each Entropy sample taken
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* */
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val = sec_in32(&rng->rtsdctl);
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val = (val & ~RTSDCTL_ENT_DLY_MASK) |
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(ent_delay << RTSDCTL_ENT_DLY_SHIFT);
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sec_out32(&rng->rtsdctl, val);
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/* min. freq. count, equal to 1/4 of the entropy sample length */
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sec_out32(&rng->rtfreqmin, ent_delay >> 2);
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/* disable maximum frequency count */
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sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
|
|
/* read the control register */
|
|
val = sec_in32(&rng->rtmctl);
|
|
/*
|
|
* select raw sampling in both entropy shifter
|
|
* and statistical checker
|
|
*/
|
|
sec_setbits32(&val, RTMCTL_SAMP_MODE_RAW_ES_SC);
|
|
/* put RNG4 into run mode */
|
|
sec_clrbits32(&val, RTMCTL_PRGM);
|
|
/* write back the control register */
|
|
sec_out32(&rng->rtmctl, val);
|
|
}
|
|
|
|
static int rng_init(void)
|
|
{
|
|
int ret, ent_delay = RTSDCTL_ENT_DLY_MIN;
|
|
ccsr_sec_t __iomem *sec =
|
|
(ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
|
|
struct rng4tst __iomem *rng =
|
|
(struct rng4tst __iomem *)&sec->rng;
|
|
|
|
u32 rdsta = sec_in32(&rng->rdsta);
|
|
|
|
/* Check if RNG state 0 handler is already instantiated */
|
|
if (rdsta & RNG_STATE0_HANDLE_INSTANTIATED)
|
|
return 0;
|
|
|
|
do {
|
|
/*
|
|
* If either of the SH's were instantiated by somebody else
|
|
* then it is assumed that the entropy
|
|
* parameters are properly set and thus the function
|
|
* setting these (kick_trng(...)) is skipped.
|
|
* Also, if a handle was instantiated, do not change
|
|
* the TRNG parameters.
|
|
*/
|
|
kick_trng(ent_delay);
|
|
ent_delay += 400;
|
|
/*
|
|
* if instantiate_rng(...) fails, the loop will rerun
|
|
* and the kick_trng(...) function will modfiy the
|
|
* upper and lower limits of the entropy sampling
|
|
* interval, leading to a sucessful initialization of
|
|
* the RNG.
|
|
*/
|
|
ret = instantiate_rng();
|
|
} while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
|
|
if (ret) {
|
|
printf("RNG: Failed to instantiate RNG\n");
|
|
return ret;
|
|
}
|
|
|
|
/* Enable RDB bit so that RNG works faster */
|
|
sec_setbits32(&sec->scfgr, SEC_SCFGR_RDBENABLE);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int sec_init(void)
|
|
{
|
|
ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
|
|
uint32_t mcr = sec_in32(&sec->mcfgr);
|
|
int ret = 0;
|
|
|
|
mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
|
|
#ifdef CONFIG_PHYS_64BIT
|
|
mcr |= (1 << MCFGR_PS_SHIFT);
|
|
#endif
|
|
sec_out32(&sec->mcfgr, mcr);
|
|
|
|
ret = jr_init();
|
|
if (ret < 0) {
|
|
printf("SEC initialization failed\n");
|
|
return -1;
|
|
}
|
|
|
|
if (get_rng_vid() >= 4) {
|
|
if (rng_init() < 0) {
|
|
printf("RNG instantiation failed\n");
|
|
return -1;
|
|
}
|
|
printf("SEC: RNG instantiated\n");
|
|
}
|
|
|
|
return ret;
|
|
}
|