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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
243 lines
6.2 KiB
C
243 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Functions related to OMAP3 SDRC.
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*
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* This file has been created after exctracting and consolidating
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* the SDRC related content from mem.c and board.c, also created
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* generic init function (mem_init).
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*
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* Copyright (C) 2004-2010
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* Texas Instruments Incorporated - http://www.ti.com/
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*
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* Copyright (C) 2011
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* Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
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*
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* Author :
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* Vaibhav Hiremath <hvaibhav@ti.com>
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*
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* Original implementation by (mem.c, board.c) :
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* Sunil Kumar <sunilsaini05@gmail.com>
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* Shashi Ranjan <shashiranjanmca05@gmail.com>
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* Manikandan Pillai <mani.pillai@ti.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern omap3_sysinfo sysinfo;
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static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
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/*
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* is_mem_sdr -
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* - Return 1 if mem type in use is SDR
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*/
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u32 is_mem_sdr(void)
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{
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if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
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return 1;
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return 0;
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}
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/*
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* make_cs1_contiguous -
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* - When we have CS1 populated we want to have it mapped after cs0 to allow
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* command line mem=xyz use all memory with out discontinuous support
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* compiled in. We could do it in the ATAG, but there really is two banks...
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*/
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void make_cs1_contiguous(void)
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{
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u32 size, a_add_low, a_add_high;
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size = get_sdr_cs_size(CS0);
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size >>= 25; /* divide by 32 MiB to find size to offset CS1 */
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a_add_high = (size & 3) << 8; /* set up low field */
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a_add_low = (size & 0x3C) >> 2; /* set up high field */
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writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
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}
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/*
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* get_sdr_cs_size -
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* - Get size of chip select 0/1
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*/
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u32 get_sdr_cs_size(u32 cs)
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{
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u32 size;
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/* get ram size field */
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size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
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size &= 0x3FF; /* remove unwanted bits */
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size <<= 21; /* multiply by 2 MiB to find size in MB */
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return size;
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}
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/*
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* get_sdr_cs_offset -
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* - Get offset of cs from cs0 start
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*/
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u32 get_sdr_cs_offset(u32 cs)
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{
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u32 offset;
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if (!cs)
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return 0;
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offset = readl(&sdrc_base->cs_cfg);
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offset = (offset & 15) << 27 | (offset & 0x300) << 17;
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return offset;
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}
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/*
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* write_sdrc_timings -
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* - Takes CS and associated timings and initalize SDRAM
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* - Test CS to make sure it's OK for use
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*/
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static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
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struct board_sdrc_timings *timings)
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{
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/* Setup timings we got from the board. */
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writel(timings->mcfg, &sdrc_base->cs[cs].mcfg);
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writel(timings->ctrla, &sdrc_actim_base->ctrla);
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writel(timings->ctrlb, &sdrc_actim_base->ctrlb);
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writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
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writel(CMD_NOP, &sdrc_base->cs[cs].manual);
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writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
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writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
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writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
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writel(timings->mr, &sdrc_base->cs[cs].mr);
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/*
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* Test ram in this bank
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* Disable if bad or not present
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*/
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if (!mem_ok(cs))
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writel(0, &sdrc_base->cs[cs].mcfg);
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}
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/*
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* do_sdrc_init -
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* - Code called once in C-Stack only context for CS0 and with early being
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* true and a possible 2nd time depending on memory configuration from
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* stack+global context.
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*/
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void do_sdrc_init(u32 cs, u32 early)
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{
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struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
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struct board_sdrc_timings timings;
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sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
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sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
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/* set some default timings */
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timings.sharing = SDRC_SHARING;
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/*
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* When called in the early context this may be SPL and we will
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* need to set all of the timings. This ends up being board
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* specific so we call a helper function to take care of this
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* for us. Otherwise, to be safe, we need to copy the settings
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* from the first bank to the second. We will setup CS0,
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* then set cs_cfg to the appropriate value then try and
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* setup CS1.
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*/
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#ifdef CONFIG_SPL_BUILD
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/* set/modify board-specific timings */
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get_board_mem_timings(&timings);
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#endif
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if (early) {
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/* reset sdrc controller */
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writel(SOFTRESET, &sdrc_base->sysconfig);
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wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
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12000000);
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writel(0, &sdrc_base->sysconfig);
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/* setup sdrc to ball mux */
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writel(timings.sharing, &sdrc_base->sharing);
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/* Disable Power Down of CKE because of 1 CKE on combo part */
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writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
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&sdrc_base->power);
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writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
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sdelay(0x20000);
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#ifdef CONFIG_SPL_BUILD
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write_sdrc_timings(CS0, sdrc_actim_base0, &timings);
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make_cs1_contiguous();
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write_sdrc_timings(CS1, sdrc_actim_base1, &timings);
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#endif
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}
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/*
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* If we aren't using SPL we have been loaded by some
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* other means which may not have correctly initialized
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* both CS0 and CS1 (such as some older versions of x-loader)
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* so we may be asked now to setup CS1.
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*/
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if (cs == CS1) {
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timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg),
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timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);
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timings.ctrla = readl(&sdrc_actim_base0->ctrla);
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timings.ctrlb = readl(&sdrc_actim_base0->ctrlb);
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timings.mr = readl(&sdrc_base->cs[CS0].mr);
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write_sdrc_timings(cs, sdrc_actim_base1, &timings);
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}
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}
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/*
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* dram_init -
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* - Sets uboots idea of sdram size
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*/
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int dram_init(void)
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{
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unsigned int size0 = 0, size1 = 0;
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size0 = get_sdr_cs_size(CS0);
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/*
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* We always need to have cs_cfg point at where the second
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* bank would be, if present. Failure to do so can lead to
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* strange situations where memory isn't detected and
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* configured correctly. CS0 will already have been setup
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* at this point.
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*/
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make_cs1_contiguous();
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do_sdrc_init(CS1, NOT_EARLY);
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size1 = get_sdr_cs_size(CS1);
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gd->ram_size = size0 + size1;
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return 0;
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}
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int dram_init_banksize(void)
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{
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unsigned int size0 = 0, size1 = 0;
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size0 = get_sdr_cs_size(CS0);
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size1 = get_sdr_cs_size(CS1);
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = size0;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
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gd->bd->bi_dram[1].size = size1;
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return 0;
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}
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/*
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* mem_init -
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* - Init the sdrc chip,
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* - Selects CS0 and CS1,
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*/
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void mem_init(void)
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{
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/* only init up first bank here */
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do_sdrc_init(CS0, EARLY_INIT);
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}
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