mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
129 lines
4.2 KiB
C
129 lines
4.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* https://spdx.org/licenses
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*/
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#ifndef __BOARD_H__
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#define __BOARD_H__
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#include <asm/arch/soc.h>
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/** Reg offsets */
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#define RST_BOOT 0x87E006001600ULL
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#define CPC_BOOT_OWNERX(a) 0x86D000000160ULL + (8 * (a))
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/** Structure definitions */
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/**
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* Register (NCB32b) cpc_boot_owner#
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*
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* CPC Boot Owner Registers These registers control an external arbiter
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* for the boot device (SPI/eMMC) across multiple external devices. There
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* is a register for each requester: _ \<0\> - SCP - reset on
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* SCP reset _ \<1\> - MCP - reset on MCP reset _ \<2\> - AP
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* Secure - reset on core reset _ \<3\> - AP Nonsecure - reset on core
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* reset These register is only writable to the corresponding
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* requestor(s) permitted with CPC_PERMIT.
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*/
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union cpc_boot_ownerx {
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u32 u;
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struct cpc_boot_ownerx_s {
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u32 boot_req : 1;
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u32 reserved_1_7 : 7;
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u32 boot_wait : 1;
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u32 reserved_9_31 : 23;
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} s;
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};
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/**
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* Register (RSL) rst_boot
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*
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* RST Boot Register This register is not accessible through ROM scripts;
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* see SCR_WRITE32_S[ADDR].
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*/
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union rst_boot {
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u64 u;
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struct rst_boot_s {
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u64 rboot_pin : 1;
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u64 rboot : 1;
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u64 reserved_2_32 : 31;
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u64 pnr_mul : 6;
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u64 reserved_39 : 1;
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u64 c_mul : 7;
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u64 reserved_47_52 : 6;
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u64 gpio_ejtag : 1;
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u64 mcp_jtagdis : 1;
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u64 dis_scan : 1;
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u64 dis_huk : 1;
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u64 vrm_err : 1;
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u64 jt_tstmode : 1;
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u64 ckill_ppdis : 1;
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u64 trusted_mode : 1;
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u64 reserved_61_62 : 2;
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u64 chipkill : 1;
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} s;
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struct rst_boot_cn96xx {
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u64 rboot_pin : 1;
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u64 rboot : 1;
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u64 reserved_2_23 : 22;
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u64 cpt_mul : 7;
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u64 reserved_31_32 : 2;
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u64 pnr_mul : 6;
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u64 reserved_39 : 1;
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u64 c_mul : 7;
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u64 reserved_47_52 : 6;
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u64 gpio_ejtag : 1;
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u64 mcp_jtagdis : 1;
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u64 dis_scan : 1;
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u64 dis_huk : 1;
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u64 vrm_err : 1;
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u64 reserved_58_59 : 2;
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u64 trusted_mode : 1;
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u64 scp_jtagdis : 1;
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u64 jtagdis : 1;
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u64 chipkill : 1;
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} cn96xx;
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struct rst_boot_cnf95xx {
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u64 rboot_pin : 1;
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u64 rboot : 1;
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u64 reserved_2_7 : 6;
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u64 bphy_mul : 7;
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u64 reserved_15 : 1;
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u64 dsp_mul : 7;
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u64 reserved_23 : 1;
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u64 cpt_mul : 7;
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u64 reserved_31_32 : 2;
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u64 pnr_mul : 6;
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u64 reserved_39 : 1;
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u64 c_mul : 7;
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u64 reserved_47_52 : 6;
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u64 gpio_ejtag : 1;
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u64 mcp_jtagdis : 1;
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u64 dis_scan : 1;
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u64 dis_huk : 1;
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u64 vrm_err : 1;
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u64 reserved_58_59 : 2;
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u64 trusted_mode : 1;
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u64 scp_jtagdis : 1;
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u64 jtagdis : 1;
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u64 chipkill : 1;
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} cnf95xx;
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};
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extern unsigned long fdt_base_addr;
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/** Function definitions */
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void mem_map_fill(void);
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int fdt_get_board_mac_cnt(void);
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u64 fdt_get_board_mac_addr(void);
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const char *fdt_get_board_model(void);
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const char *fdt_get_board_serial(void);
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const char *fdt_get_board_revision(void);
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void octeontx2_board_get_mac_addr(u8 index, u8 *mac_addr);
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void board_acquire_flash_arb(bool acquire);
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void cgx_intf_shutdown(void);
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#endif /* __BOARD_H__ */
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