mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
387d321add
Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org>
124 lines
4.0 KiB
C
124 lines
4.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* https://spdx.org/licenses
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*/
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#ifndef __BOARD_H__
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#define __BOARD_H__
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#include <asm/arch/soc.h>
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#define MAX_LMAC_PER_BGX 4
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#define LMAC_CNT MAX_LMAC_PER_BGX
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#if defined(CONFIG_TARGET_OCTEONTX_81XX)
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/** Maximum number of BGX interfaces per CPU node */
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#define MAX_BGX_PER_NODE 3
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#define OCTEONTX_XCV /* RGMII Interface */
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#elif defined(CONFIG_TARGET_OCTEONTX_83XX)
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/** Maximum number of BGX interfaces per CPU node */
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#define MAX_BGX_PER_NODE 4
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#endif
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/** Reg offsets */
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#define RST_BOOT 0x87E006001600ULL
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/** Structure definitions */
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/**
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* Register (RSL) rst_boot
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*
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* RST Boot Register This register is not accessible through ROM scripts;
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* see SCR_WRITE32_S[ADDR].
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*/
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union rst_boot {
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u64 u;
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struct rst_boot_s {
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u64 rboot_pin : 1;
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u64 rboot : 1;
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u64 reserved_2_32 : 31;
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u64 pnr_mul : 6;
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u64 reserved_39 : 1;
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u64 c_mul : 7;
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u64 reserved_47_52 : 6;
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u64 gpio_ejtag : 1;
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u64 mcp_jtagdis : 1;
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u64 dis_scan : 1;
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u64 dis_huk : 1;
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u64 vrm_err : 1;
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u64 jt_tstmode : 1;
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u64 ckill_ppdis : 1;
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u64 trusted_mode : 1;
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u64 reserved_61_62 : 2;
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u64 chipkill : 1;
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} s;
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struct rst_boot_cn81xx {
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u64 rboot_pin : 1;
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u64 rboot : 1;
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u64 lboot : 10;
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u64 lboot_ext23 : 6;
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u64 lboot_ext45 : 6;
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u64 lboot_jtg : 1;
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u64 lboot_ckill : 1;
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u64 reserved_26_29 : 4;
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u64 lboot_oci : 3;
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u64 pnr_mul : 6;
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u64 reserved_39 : 1;
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u64 c_mul : 7;
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u64 reserved_47_54 : 8;
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u64 dis_scan : 1;
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u64 dis_huk : 1;
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u64 vrm_err : 1;
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u64 jt_tstmode : 1;
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u64 ckill_ppdis : 1;
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u64 trusted_mode : 1;
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u64 ejtagdis : 1;
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u64 jtcsrdis : 1;
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u64 chipkill : 1;
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} cn81xx;
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struct rst_boot_cn83xx {
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u64 rboot_pin : 1;
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u64 rboot : 1;
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u64 lboot : 10;
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u64 lboot_ext23 : 6;
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u64 lboot_ext45 : 6;
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u64 lboot_jtg : 1;
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u64 lboot_ckill : 1;
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u64 lboot_pf_flr : 4;
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u64 lboot_oci : 3;
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u64 pnr_mul : 6;
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u64 reserved_39 : 1;
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u64 c_mul : 7;
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u64 reserved_47_54 : 8;
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u64 dis_scan : 1;
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u64 dis_huk : 1;
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u64 vrm_err : 1;
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u64 jt_tstmode : 1;
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u64 ckill_ppdis : 1;
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u64 trusted_mode : 1;
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u64 ejtagdis : 1;
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u64 jtcsrdis : 1;
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u64 chipkill : 1;
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} cn83xx;
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};
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extern unsigned long fdt_base_addr;
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/** Function definitions */
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void mem_map_fill(void);
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int octeontx_board_has_pmp(void);
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const char *fdt_get_board_model(void);
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const char *fdt_get_board_serial(void);
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const char *fdt_get_board_revision(void);
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void fdt_parse_phy_info(void);
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void fdt_board_get_ethaddr(int bgx, int lmac, unsigned char *eth);
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void bgx_set_board_info(int bgx_id, int *mdio_bus, int *phy_addr,
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bool *autoneg_dis, bool *lmac_reg, bool *lmac_enable);
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#endif /* __BOARD_H__ */
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