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![Rajeshwari Birje](/assets/img/avatar_default.png)
This patch intends to add DDR3 initialization code for Exynos5420. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
637 lines
19 KiB
C
637 lines
19 KiB
C
/*
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* DDR3 mem setup file for board based on EXYNOS5
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*
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* Copyright (C) 2012 Samsung Electronics
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/dmc.h>
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#include <asm/arch/power.h>
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#include "common_setup.h"
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#include "exynos5_setup.h"
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#include "clock_init.h"
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#define TIMEOUT 10000
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#ifdef CONFIG_EXYNOS5250
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static void reset_phy_ctrl(void)
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{
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struct exynos5_clock *clk =
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(struct exynos5_clock *)samsung_get_base_clock();
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writel(DDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl);
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writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
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}
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int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
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int reset)
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{
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unsigned int val;
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struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
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struct exynos5_dmc *dmc;
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int i;
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phy0_ctrl = (struct exynos5_phy_control *)samsung_get_base_dmc_phy();
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phy1_ctrl = (struct exynos5_phy_control *)(samsung_get_base_dmc_phy()
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+ DMC_OFFSET);
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dmc = (struct exynos5_dmc *)samsung_get_base_dmc_ctrl();
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if (reset)
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reset_phy_ctrl();
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/* Set Impedance Output Driver */
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val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) |
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(mem->impedance << CA_CKE_DRVR_DS_OFFSET) |
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(mem->impedance << CA_CS_DRVR_DS_OFFSET) |
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(mem->impedance << CA_ADR_DRVR_DS_OFFSET);
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writel(val, &phy0_ctrl->phy_con39);
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writel(val, &phy1_ctrl->phy_con39);
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/* Set Read Latency and Burst Length for PHY0 and PHY1 */
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val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
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(mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
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writel(val, &phy0_ctrl->phy_con42);
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writel(val, &phy1_ctrl->phy_con42);
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/* ZQ Calibration */
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if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16,
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&phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17))
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return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
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/* DQ Signal */
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writel(mem->phy0_pulld_dqs, &phy0_ctrl->phy_con14);
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writel(mem->phy1_pulld_dqs, &phy1_ctrl->phy_con14);
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writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
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| (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT),
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&dmc->concontrol);
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update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
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/* DQS Signal */
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writel(mem->phy0_dqs, &phy0_ctrl->phy_con4);
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writel(mem->phy1_dqs, &phy1_ctrl->phy_con4);
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writel(mem->phy0_dq, &phy0_ctrl->phy_con6);
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writel(mem->phy1_dq, &phy1_ctrl->phy_con6);
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writel(mem->phy0_tFS, &phy0_ctrl->phy_con10);
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writel(mem->phy1_tFS, &phy1_ctrl->phy_con10);
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val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) |
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(mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
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(mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
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(mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
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writel(val, &phy0_ctrl->phy_con12);
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writel(val, &phy1_ctrl->phy_con12);
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/* Start DLL locking */
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writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
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&phy0_ctrl->phy_con12);
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writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
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&phy1_ctrl->phy_con12);
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update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
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writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
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&dmc->concontrol);
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/* Memory Channel Inteleaving Size */
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writel(mem->iv_size, &dmc->ivcontrol);
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writel(mem->memconfig, &dmc->memconfig0);
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writel(mem->memconfig, &dmc->memconfig1);
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writel(mem->membaseconfig0, &dmc->membaseconfig0);
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writel(mem->membaseconfig1, &dmc->membaseconfig1);
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/* Precharge Configuration */
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writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
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&dmc->prechconfig);
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/* Power Down mode Configuration */
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writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |
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mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT,
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&dmc->pwrdnconfig);
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/* TimingRow, TimingData, TimingPower and Timingaref
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* values as per Memory AC parameters
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*/
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writel(mem->timing_ref, &dmc->timingref);
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writel(mem->timing_row, &dmc->timingrow);
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writel(mem->timing_data, &dmc->timingdata);
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writel(mem->timing_power, &dmc->timingpower);
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/* Send PALL command */
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dmc_config_prech(mem, &dmc->directcmd);
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/* Send NOP, MRS and ZQINIT commands */
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dmc_config_mrs(mem, &dmc->directcmd);
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if (mem->gate_leveling_enable) {
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val = PHY_CON0_RESET_VAL;
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val |= P0_CMD_EN;
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writel(val, &phy0_ctrl->phy_con0);
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writel(val, &phy1_ctrl->phy_con0);
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val = PHY_CON2_RESET_VAL;
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val |= INIT_DESKEW_EN;
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writel(val, &phy0_ctrl->phy_con2);
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writel(val, &phy1_ctrl->phy_con2);
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val = PHY_CON0_RESET_VAL;
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val |= P0_CMD_EN;
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val |= BYTE_RDLVL_EN;
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writel(val, &phy0_ctrl->phy_con0);
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writel(val, &phy1_ctrl->phy_con0);
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val = (mem->ctrl_start_point <<
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PHY_CON12_CTRL_START_POINT_SHIFT) |
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(mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
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(mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |
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(mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
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(mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
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writel(val, &phy0_ctrl->phy_con12);
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writel(val, &phy1_ctrl->phy_con12);
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val = PHY_CON2_RESET_VAL;
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val |= INIT_DESKEW_EN;
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val |= RDLVL_GATE_EN;
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writel(val, &phy0_ctrl->phy_con2);
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writel(val, &phy1_ctrl->phy_con2);
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val = PHY_CON0_RESET_VAL;
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val |= P0_CMD_EN;
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val |= BYTE_RDLVL_EN;
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val |= CTRL_SHGATE;
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writel(val, &phy0_ctrl->phy_con0);
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writel(val, &phy1_ctrl->phy_con0);
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val = PHY_CON1_RESET_VAL;
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val &= ~(CTRL_GATEDURADJ_MASK);
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writel(val, &phy0_ctrl->phy_con1);
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writel(val, &phy1_ctrl->phy_con1);
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writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config);
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i = TIMEOUT;
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while ((readl(&dmc->phystatus) &
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(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) !=
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(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) {
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/*
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* TODO(waihong): Comment on how long this take to
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* timeout
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*/
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sdelay(100);
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i--;
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}
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if (!i)
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return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
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writel(CTRL_RDLVL_GATE_DISABLE, &dmc->rdlvl_config);
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writel(0, &phy0_ctrl->phy_con14);
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writel(0, &phy1_ctrl->phy_con14);
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val = (mem->ctrl_start_point <<
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PHY_CON12_CTRL_START_POINT_SHIFT) |
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(mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
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(mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |
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(mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
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(mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
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(mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
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writel(val, &phy0_ctrl->phy_con12);
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writel(val, &phy1_ctrl->phy_con12);
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update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
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}
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/* Send PALL command */
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dmc_config_prech(mem, &dmc->directcmd);
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writel(mem->memcontrol, &dmc->memcontrol);
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/* Set DMC Concontrol and enable auto-refresh counter */
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writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
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| (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol);
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return 0;
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}
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#endif
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#ifdef CONFIG_EXYNOS5420
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int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
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int reset)
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{
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struct exynos5420_clock *clk =
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(struct exynos5420_clock *)samsung_get_base_clock();
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struct exynos5420_power *power =
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(struct exynos5420_power *)samsung_get_base_power();
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struct exynos5420_phy_control *phy0_ctrl, *phy1_ctrl;
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struct exynos5420_dmc *drex0, *drex1;
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struct exynos5420_tzasc *tzasc0, *tzasc1;
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uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1;
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int chip;
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int i;
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phy0_ctrl = (struct exynos5420_phy_control *)samsung_get_base_dmc_phy();
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phy1_ctrl = (struct exynos5420_phy_control *)(samsung_get_base_dmc_phy()
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+ DMC_OFFSET);
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drex0 = (struct exynos5420_dmc *)samsung_get_base_dmc_ctrl();
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drex1 = (struct exynos5420_dmc *)(samsung_get_base_dmc_ctrl()
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+ DMC_OFFSET);
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tzasc0 = (struct exynos5420_tzasc *)samsung_get_base_dmc_tzasc();
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tzasc1 = (struct exynos5420_tzasc *)(samsung_get_base_dmc_tzasc()
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+ DMC_OFFSET);
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/* Enable PAUSE for DREX */
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setbits_le32(&clk->pause, ENABLE_BIT);
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/* Enable BYPASS mode */
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setbits_le32(&clk->bpll_con1, BYPASS_EN);
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writel(MUX_BPLL_SEL_FOUTBPLL, &clk->src_cdrex);
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do {
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val = readl(&clk->mux_stat_cdrex);
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val &= BPLL_SEL_MASK;
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} while (val != FOUTBPLL);
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clrbits_le32(&clk->bpll_con1, BYPASS_EN);
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/* Specify the DDR memory type as DDR3 */
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val = readl(&phy0_ctrl->phy_con0);
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val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
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val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);
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writel(val, &phy0_ctrl->phy_con0);
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val = readl(&phy1_ctrl->phy_con0);
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val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
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val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);
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writel(val, &phy1_ctrl->phy_con0);
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/* Set Read Latency and Burst Length for PHY0 and PHY1 */
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val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
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(mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
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writel(val, &phy0_ctrl->phy_con42);
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writel(val, &phy1_ctrl->phy_con42);
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val = readl(&phy0_ctrl->phy_con26);
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val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
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val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
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writel(val, &phy0_ctrl->phy_con26);
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val = readl(&phy1_ctrl->phy_con26);
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val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
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val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
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writel(val, &phy1_ctrl->phy_con26);
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/*
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* Set Driver strength for CK, CKE, CS & CA to 0x7
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* Set Driver strength for Data Slice 0~3 to 0x7
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*/
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val = (0x7 << CA_CK_DRVR_DS_OFFSET) | (0x7 << CA_CKE_DRVR_DS_OFFSET) |
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(0x7 << CA_CS_DRVR_DS_OFFSET) | (0x7 << CA_ADR_DRVR_DS_OFFSET);
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val |= (0x7 << DA_3_DS_OFFSET) | (0x7 << DA_2_DS_OFFSET) |
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(0x7 << DA_1_DS_OFFSET) | (0x7 << DA_0_DS_OFFSET);
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writel(val, &phy0_ctrl->phy_con39);
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writel(val, &phy1_ctrl->phy_con39);
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/* ZQ Calibration */
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if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16,
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&phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17))
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return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
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clrbits_le32(&phy0_ctrl->phy_con16, ZQ_CLK_DIV_EN);
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clrbits_le32(&phy1_ctrl->phy_con16, ZQ_CLK_DIV_EN);
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/* DQ Signal */
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val = readl(&phy0_ctrl->phy_con14);
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val |= mem->phy0_pulld_dqs;
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writel(val, &phy0_ctrl->phy_con14);
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val = readl(&phy1_ctrl->phy_con14);
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val |= mem->phy1_pulld_dqs;
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writel(val, &phy1_ctrl->phy_con14);
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val = MEM_TERM_EN | PHY_TERM_EN;
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writel(val, &drex0->phycontrol0);
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writel(val, &drex1->phycontrol0);
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writel(mem->concontrol |
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(mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
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(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
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&drex0->concontrol);
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writel(mem->concontrol |
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(mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
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(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
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&drex1->concontrol);
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do {
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val = readl(&drex0->phystatus);
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} while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
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do {
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val = readl(&drex1->phystatus);
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} while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
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clrbits_le32(&drex0->concontrol, DFI_INIT_START);
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clrbits_le32(&drex1->concontrol, DFI_INIT_START);
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update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3);
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update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3);
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/*
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* Set Base Address:
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* 0x2000_0000 ~ 0x5FFF_FFFF
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* 0x6000_0000 ~ 0x9FFF_FFFF
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*/
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/* MEMBASECONFIG0 */
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val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_0) |
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DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK);
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writel(val, &tzasc0->membaseconfig0);
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writel(val, &tzasc1->membaseconfig0);
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/* MEMBASECONFIG1 */
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val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_1) |
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DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK);
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writel(val, &tzasc0->membaseconfig1);
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writel(val, &tzasc1->membaseconfig1);
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/*
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* Memory Channel Inteleaving Size
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* Ares Channel interleaving = 128 bytes
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*/
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/* MEMCONFIG0/1 */
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writel(mem->memconfig, &tzasc0->memconfig0);
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writel(mem->memconfig, &tzasc1->memconfig0);
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writel(mem->memconfig, &tzasc0->memconfig1);
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writel(mem->memconfig, &tzasc1->memconfig1);
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/* Precharge Configuration */
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writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
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&drex0->prechconfig0);
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writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
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&drex1->prechconfig0);
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/*
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* TimingRow, TimingData, TimingPower and Timingaref
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* values as per Memory AC parameters
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*/
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writel(mem->timing_ref, &drex0->timingref);
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writel(mem->timing_ref, &drex1->timingref);
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writel(mem->timing_row, &drex0->timingrow0);
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writel(mem->timing_row, &drex1->timingrow0);
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writel(mem->timing_data, &drex0->timingdata0);
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writel(mem->timing_data, &drex1->timingdata0);
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writel(mem->timing_power, &drex0->timingpower0);
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writel(mem->timing_power, &drex1->timingpower0);
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if (reset) {
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/*
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* Send NOP, MRS and ZQINIT commands
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* Sending MRS command will reset the DRAM. We should not be
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* reseting the DRAM after resume, this will lead to memory
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* corruption as DRAM content is lost after DRAM reset
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*/
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dmc_config_mrs(mem, &drex0->directcmd);
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dmc_config_mrs(mem, &drex1->directcmd);
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} else {
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/*
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* During Suspend-Resume & S/W-Reset, as soon as PMU releases
|
|
* pad retention, CKE goes high. This causes memory contents
|
|
* not to be retained during DRAM initialization. Therfore,
|
|
* there is a new control register(0x100431e8[28]) which lets us
|
|
* release pad retention and retain the memory content until the
|
|
* initialization is complete.
|
|
*/
|
|
writel(PAD_RETENTION_DRAM_COREBLK_VAL,
|
|
&power->pad_retention_dram_coreblk_option);
|
|
do {
|
|
val = readl(&power->pad_retention_dram_status);
|
|
} while (val != 0x1);
|
|
|
|
/*
|
|
* CKE PAD retention disables DRAM self-refresh mode.
|
|
* Send auto refresh command for DRAM refresh.
|
|
*/
|
|
for (i = 0; i < 128; i++) {
|
|
for (chip = 0; chip < mem->chips_to_configure; chip++) {
|
|
writel(DIRECT_CMD_REFA |
|
|
(chip << DIRECT_CMD_CHIP_SHIFT),
|
|
&drex0->directcmd);
|
|
writel(DIRECT_CMD_REFA |
|
|
(chip << DIRECT_CMD_CHIP_SHIFT),
|
|
&drex1->directcmd);
|
|
}
|
|
}
|
|
}
|
|
|
|
if (mem->gate_leveling_enable) {
|
|
writel(PHY_CON0_RESET_VAL, &phy0_ctrl->phy_con0);
|
|
writel(PHY_CON0_RESET_VAL, &phy1_ctrl->phy_con0);
|
|
|
|
setbits_le32(&phy0_ctrl->phy_con0, P0_CMD_EN);
|
|
setbits_le32(&phy1_ctrl->phy_con0, P0_CMD_EN);
|
|
|
|
val = PHY_CON2_RESET_VAL;
|
|
val |= INIT_DESKEW_EN;
|
|
writel(val, &phy0_ctrl->phy_con2);
|
|
writel(val, &phy1_ctrl->phy_con2);
|
|
|
|
val = readl(&phy0_ctrl->phy_con1);
|
|
val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
|
|
writel(val, &phy0_ctrl->phy_con1);
|
|
|
|
val = readl(&phy1_ctrl->phy_con1);
|
|
val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
|
|
writel(val, &phy1_ctrl->phy_con1);
|
|
|
|
n_lock_r = readl(&phy0_ctrl->phy_con13);
|
|
n_lock_w_phy0 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2;
|
|
n_lock_r = readl(&phy0_ctrl->phy_con12);
|
|
n_lock_r &= ~CTRL_DLL_ON;
|
|
n_lock_r |= n_lock_w_phy0;
|
|
writel(n_lock_r, &phy0_ctrl->phy_con12);
|
|
|
|
n_lock_r = readl(&phy1_ctrl->phy_con13);
|
|
n_lock_w_phy1 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2;
|
|
n_lock_r = readl(&phy1_ctrl->phy_con12);
|
|
n_lock_r &= ~CTRL_DLL_ON;
|
|
n_lock_r |= n_lock_w_phy1;
|
|
writel(n_lock_r, &phy1_ctrl->phy_con12);
|
|
|
|
val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
|
|
for (chip = 0; chip < mem->chips_to_configure; chip++) {
|
|
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
|
|
&drex0->directcmd);
|
|
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
|
|
&drex1->directcmd);
|
|
}
|
|
|
|
setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN);
|
|
setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN);
|
|
|
|
setbits_le32(&phy0_ctrl->phy_con0, CTRL_SHGATE);
|
|
setbits_le32(&phy1_ctrl->phy_con0, CTRL_SHGATE);
|
|
|
|
val = readl(&phy0_ctrl->phy_con1);
|
|
val &= ~(CTRL_GATEDURADJ_MASK);
|
|
writel(val, &phy0_ctrl->phy_con1);
|
|
|
|
val = readl(&phy1_ctrl->phy_con1);
|
|
val &= ~(CTRL_GATEDURADJ_MASK);
|
|
writel(val, &phy1_ctrl->phy_con1);
|
|
|
|
writel(CTRL_RDLVL_GATE_ENABLE, &drex0->rdlvl_config);
|
|
i = TIMEOUT;
|
|
while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) !=
|
|
RDLVL_COMPLETE_CHO) && (i > 0)) {
|
|
/*
|
|
* TODO(waihong): Comment on how long this take to
|
|
* timeout
|
|
*/
|
|
sdelay(100);
|
|
i--;
|
|
}
|
|
if (!i)
|
|
return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
|
|
writel(CTRL_RDLVL_GATE_DISABLE, &drex0->rdlvl_config);
|
|
|
|
writel(CTRL_RDLVL_GATE_ENABLE, &drex1->rdlvl_config);
|
|
i = TIMEOUT;
|
|
while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) !=
|
|
RDLVL_COMPLETE_CHO) && (i > 0)) {
|
|
/*
|
|
* TODO(waihong): Comment on how long this take to
|
|
* timeout
|
|
*/
|
|
sdelay(100);
|
|
i--;
|
|
}
|
|
if (!i)
|
|
return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
|
|
writel(CTRL_RDLVL_GATE_DISABLE, &drex1->rdlvl_config);
|
|
|
|
writel(0, &phy0_ctrl->phy_con14);
|
|
writel(0, &phy1_ctrl->phy_con14);
|
|
|
|
val = (0x3 << DIRECT_CMD_BANK_SHIFT);
|
|
for (chip = 0; chip < mem->chips_to_configure; chip++) {
|
|
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
|
|
&drex0->directcmd);
|
|
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
|
|
&drex1->directcmd);
|
|
}
|
|
|
|
if (mem->read_leveling_enable) {
|
|
/* Set Read DQ Calibration */
|
|
val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
|
|
for (chip = 0; chip < mem->chips_to_configure; chip++) {
|
|
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
|
|
&drex0->directcmd);
|
|
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
|
|
&drex1->directcmd);
|
|
}
|
|
|
|
val = readl(&phy0_ctrl->phy_con1);
|
|
val |= READ_LEVELLING_DDR3;
|
|
writel(val, &phy0_ctrl->phy_con1);
|
|
val = readl(&phy1_ctrl->phy_con1);
|
|
val |= READ_LEVELLING_DDR3;
|
|
writel(val, &phy1_ctrl->phy_con1);
|
|
|
|
val = readl(&phy0_ctrl->phy_con2);
|
|
val |= (RDLVL_EN | RDLVL_INCR_ADJ);
|
|
writel(val, &phy0_ctrl->phy_con2);
|
|
val = readl(&phy1_ctrl->phy_con2);
|
|
val |= (RDLVL_EN | RDLVL_INCR_ADJ);
|
|
writel(val, &phy1_ctrl->phy_con2);
|
|
|
|
setbits_le32(&drex0->rdlvl_config,
|
|
CTRL_RDLVL_DATA_ENABLE);
|
|
i = TIMEOUT;
|
|
while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO)
|
|
!= RDLVL_COMPLETE_CHO) && (i > 0)) {
|
|
/*
|
|
* TODO(waihong): Comment on how long this take
|
|
* to timeout
|
|
*/
|
|
sdelay(100);
|
|
i--;
|
|
}
|
|
if (!i)
|
|
return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
|
|
|
|
clrbits_le32(&drex0->rdlvl_config,
|
|
CTRL_RDLVL_DATA_ENABLE);
|
|
setbits_le32(&drex1->rdlvl_config,
|
|
CTRL_RDLVL_DATA_ENABLE);
|
|
i = TIMEOUT;
|
|
while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO)
|
|
!= RDLVL_COMPLETE_CHO) && (i > 0)) {
|
|
/*
|
|
* TODO(waihong): Comment on how long this take
|
|
* to timeout
|
|
*/
|
|
sdelay(100);
|
|
i--;
|
|
}
|
|
if (!i)
|
|
return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
|
|
|
|
clrbits_le32(&drex1->rdlvl_config,
|
|
CTRL_RDLVL_DATA_ENABLE);
|
|
|
|
val = (0x3 << DIRECT_CMD_BANK_SHIFT);
|
|
for (chip = 0; chip < mem->chips_to_configure; chip++) {
|
|
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
|
|
&drex0->directcmd);
|
|
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
|
|
&drex1->directcmd);
|
|
}
|
|
|
|
update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3);
|
|
update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3);
|
|
}
|
|
|
|
/* Common Settings for Leveling */
|
|
val = PHY_CON12_RESET_VAL;
|
|
writel((val + n_lock_w_phy0), &phy0_ctrl->phy_con12);
|
|
writel((val + n_lock_w_phy1), &phy1_ctrl->phy_con12);
|
|
|
|
setbits_le32(&phy0_ctrl->phy_con2, DLL_DESKEW_EN);
|
|
setbits_le32(&phy1_ctrl->phy_con2, DLL_DESKEW_EN);
|
|
}
|
|
|
|
/* Send PALL command */
|
|
dmc_config_prech(mem, &drex0->directcmd);
|
|
dmc_config_prech(mem, &drex1->directcmd);
|
|
|
|
writel(mem->memcontrol, &drex0->memcontrol);
|
|
writel(mem->memcontrol, &drex1->memcontrol);
|
|
|
|
/*
|
|
* Set DMC Concontrol: Enable auto-refresh counter, provide
|
|
* read data fetch cycles and enable DREX auto set powerdown
|
|
* for input buffer of I/O in none read memory state.
|
|
*/
|
|
writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
|
|
(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
|
|
DMC_CONCONTROL_IO_PD_CON(0x2),
|
|
&drex0->concontrol);
|
|
writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
|
|
(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
|
|
DMC_CONCONTROL_IO_PD_CON(0x2),
|
|
&drex1->concontrol);
|
|
|
|
/*
|
|
* Enable Clock Gating Control for DMC
|
|
* this saves around 25 mw dmc power as compared to the power
|
|
* consumption without these bits enabled
|
|
*/
|
|
setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG);
|
|
setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|