u-boot-brain/cpu/mpc85xx
Mingkai Hu 9f3243612c ppc/85xx: add boot from NAND/eSDHC/eSPI support
The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
implements these three bootup methods in a unified way - all of these
use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM
which lets us use the SPD to initialize the SDRAM.

For all three bootup methods, the bootup process can be divided into two
stages: the first stage will initialize the corresponding controller,
configure the L2SRAM, then copy the second stage image to L2SRAM and
jump to it. The second stage image is just like the general U-Boot image
to configure all the hardware and boot up to U-Boot command line.

When boot from NAND, the eLBC controller will first load the first stage
image to internal 4K RAM buffer because it's also stored on the NAND
flash. The first stage image, also call 4K NAND loader, will initialize
the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K
NAND loader's code comes from the corresponding nand_spl directory, along
with the code twisted by CONFIG_NAND_SPL.

When boot from eSDHC/eSPI, there's no such a first stage image because
the CPU ROM code does the same work. It will initialize the L2SRAM
according to the config addr/word pairs on the fixed address and
initialize the eSDHC/eSPI controller, then load the second stage image
to L2SRAM and jump to it.

The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
second stage image for all different bootup methods. It's set in the
board config file when one of the bootup methods above is selected.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-03 09:04:28 -05:00
..
commproc.c ppc/85xx: Cleanup makefile and related optional files 2009-10-03 09:04:16 -05:00
config.mk 85xx: Move to a common linker script 2009-08-28 17:12:39 -05:00
cpu_init.c ppc/85xx: add boot from NAND/eSDHC/eSPI support 2009-10-03 09:04:28 -05:00
cpu.c ppc/85xx: Clean up do_reset 2009-10-03 09:04:17 -05:00
ddr-gen1.c fsl_dma: Break out common memory initialization function 2009-07-01 23:12:01 -05:00
ddr-gen2.c rename CFG_ macros to CONFIG_SYS 2008-10-18 21:54:03 +02:00
ddr-gen3.c ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist 2009-10-03 09:04:15 -05:00
ether_fcc.c ppc/85xx: Cleanup makefile and related optional files 2009-10-03 09:04:16 -05:00
fdt.c ppc/85xx/86xx: Device tree fixup for number of cores 2009-10-03 09:04:17 -05:00
fixed_ivor.S 85xx: Add support for setting IVORs to fixed offset defaults 2009-10-03 09:04:16 -05:00
interrupts.c 85xx: Improve MPIC initialization 2009-08-28 17:12:43 -05:00
Makefile ppc/85xx: Cleanup makefile and related optional files 2009-10-03 09:04:16 -05:00
mp.c ppc/85xx: Fix bug in setup_mp code 2009-10-03 09:04:16 -05:00
mp.h 85xx: Introduce determine_mp_bootpg() helper. 2009-04-01 15:29:49 -05:00
mpc8536_serdes.c Update Freescale copyrights to remove "All Rights Reserved" 2009-07-29 09:59:22 +02:00
pci.c ppc/85xx: Cleanup makefile and related optional files 2009-10-03 09:04:16 -05:00
qe_io.c rename CFG_ macros to CONFIG_SYS 2008-10-18 21:54:03 +02:00
release.S 85xx: Add support for setting IVORs to fixed offset defaults 2009-10-03 09:04:16 -05:00
resetvec.S * Patches by Xianghua Xiao, 15 Oct 2003: 2003-10-15 23:53:47 +00:00
serial_scc.c ppc/85xx: Cleanup makefile and related optional files 2009-10-03 09:04:16 -05:00
speed.c ppc/85xx: Use CONFIG_FSL_ESDHC to enable sdhc clk 2009-10-03 09:04:15 -05:00
start.S ppc/85xx: add boot from NAND/eSDHC/eSPI support 2009-10-03 09:04:28 -05:00
tlb.c ppc/85xx: add boot from NAND/eSDHC/eSPI support 2009-10-03 09:04:28 -05:00
traps.c ppc/85xx: Remove some bogus code from external interrupt handler. 2009-10-03 09:04:27 -05:00
u-boot-nand.lds ppc/85xx: add boot from NAND/eSDHC/eSPI support 2009-10-03 09:04:28 -05:00
u-boot.lds ppc/85xx: Introduce RESET_VECTOR_ADDRESS to handle non-standard link address 2009-10-03 09:04:17 -05:00