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https://github.com/brain-hackers/u-boot-brain
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9f3183d2d6
There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
48 lines
1.2 KiB
C
48 lines
1.2 KiB
C
/*
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* Copyright 2015 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
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#define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
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#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
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#define gur_in32(a) in_le32(a)
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#define gur_out32(a, v) out_le32(a, v)
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#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
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#define gur_in32(a) in_be32(a)
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#define gur_out32(a, v) out_be32(a, v)
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#endif
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#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
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#define scfg_in32(a) in_le32(a)
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#define scfg_out32(a, v) out_le32(a, v)
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#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
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#define scfg_in32(a) in_be32(a)
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#define scfg_out32(a, v) out_be32(a, v)
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#endif
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struct cpu_type {
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char name[15];
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u32 soc_ver;
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u32 num_cores;
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};
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#define CPU_TYPE_ENTRY(n, v, nc) \
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{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
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#define SVR_WO_E 0xFFFFFE
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#define SVR_LS2045 0x870120
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#define SVR_LS2080 0x870110
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#define SVR_LS2085 0x870100
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#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
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#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
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#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
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#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
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void fsl_lsch3_early_init_f(void);
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void cpu_name(char *name);
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#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
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