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https://github.com/brain-hackers/u-boot-brain
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41e5ee54e3
This basic support for the Marvell Armada XP is base on the existing kirkwood support. Which has been generatized by moving some common files into common marvell locations. This is in preparation for the upcoming Armada XP MV78460 support. Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Luka Perkov <luka@openwrt.org>
58 lines
1.9 KiB
C
58 lines
1.9 KiB
C
/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* Header file for the Marvell's Feroceon CPU core.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_ARMADA_XP_H
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#define _ASM_ARCH_ARMADA_XP_H
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#define SOC_MV78460_ID 0x7846
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/* TCLK Core Clock definition */
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#ifndef CONFIG_SYS_TCLK
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#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
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#endif
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/* SOC specific definations */
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#define INTREG_BASE 0xd0000000
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#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
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#define SOC_REGS_PHY_BASE 0xf1000000
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#define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x)
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#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504))
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#define MVEBU_SPI_BASE (MVEBU_REGISTER(0x10600))
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#define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000))
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#define MVEBU_UART0_BASE (MVEBU_REGISTER(0x12000))
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#define MVEBU_UART1_BASE (MVEBU_REGISTER(0x12100))
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#define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000))
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#define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100))
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#define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140))
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#define MVEBU_GPIO2_BASE (MVEBU_REGISTER(0x18180))
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#define MVEBU_SYSTEM_REG_BASE (MVEBU_REGISTER(0x18200))
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#define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000))
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#define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180))
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#define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300))
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#define MVEBU_EGIGA2_BASE (MVEBU_REGISTER(0x30000))
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#define MVEBU_EGIGA3_BASE (MVEBU_REGISTER(0x34000))
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#define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000))
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#define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000))
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#define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000))
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#define SDRAM_MAX_CS 4
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#define SDRAM_ADDR_MASK 0xFF000000
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/* Armada XP GbE controller has 4 ports */
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#define MAX_MVNETA_DEVS 4
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/* Kirkwood CPU memory windows */
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#define MVCPU_WIN_CTRL_DATA CPU_WIN_CTRL_DATA
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#define MVCPU_WIN_ENABLE CPU_WIN_ENABLE
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#define MVCPU_WIN_DISABLE CPU_WIN_DISABLE
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#endif /* _ASM_ARCH_ARMADA_XP_H */
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