mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-18 16:08:53 +09:00
![]() The board uses T-topology for the four x16 DRAM chips, so remove the write-leveling from the SPL as that is only usefly on fly-by topology and can be harmful on T-topology. Also update the DRAM timing with values from calibration on multiple boards. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> |
||
---|---|---|
.. | ||
dh_imx6_spl.c | ||
dh_imx6.c | ||
Kconfig | ||
MAINTAINERS | ||
Makefile |