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https://github.com/brain-hackers/u-boot-brain
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87ac550862
SPL/TPL share the same secure_timer_init(), update to use one copy source code and update to use CONFIG_ROCKCHIP_STIMER_BASE as base address and rename to function name to rockchip_stimer_init(). Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
149 lines
4.1 KiB
C
149 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2016 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <spl_gpio.h>
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#include <asm/armv8/mmu.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/gpio.h>
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#include <asm/arch-rockchip/grf_rk3399.h>
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#include <asm/arch-rockchip/hardware.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define GRF_EMMCCORE_CON11 0xff77f02c
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#define GRF_BASE 0xff770000
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static struct mm_region rk3399_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0xf8000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xf8000000UL,
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.phys = 0xf8000000UL,
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.size = 0x08000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = rk3399_mem_map;
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#ifdef CONFIG_SPL_BUILD
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#define TIMER_END_COUNT_L 0x00
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#define TIMER_END_COUNT_H 0x04
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#define TIMER_INIT_COUNT_L 0x10
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#define TIMER_INIT_COUNT_H 0x14
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#define TIMER_CONTROL_REG 0x1c
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#define TIMER_EN 0x1
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#define TIMER_FMODE BIT(0)
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#define TIMER_RMODE BIT(1)
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void rockchip_stimer_init(void)
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{
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/* If Timer already enabled, don't re-init it */
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u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
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if (reg & TIMER_EN)
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return;
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writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_L);
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writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_H);
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writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_L);
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writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_H);
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writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + \
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TIMER_CONTROL_REG);
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}
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#endif
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int dram_init_banksize(void)
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{
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size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
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/* Reserve 0x200000 for ATF bl31 */
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gd->bd->bi_dram[0].start = 0x200000;
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gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
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return 0;
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}
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int arch_cpu_init(void)
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{
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/* We do some SoC one time setting here. */
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struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
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/* Emmc clock generator: disable the clock multipilier */
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rk_clrreg(&grf->emmccore_con[11], 0x0ff);
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return 0;
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}
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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void board_debug_uart_init(void)
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{
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#define GRF_BASE 0xff770000
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#define GPIO0_BASE 0xff720000
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#define PMUGRF_BASE 0xff320000
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struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
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#ifdef CONFIG_TARGET_CHROMEBOOK_BOB
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struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
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struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
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#endif
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#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
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/* Enable early UART0 on the RK3399 */
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rk_clrsetreg(&grf->gpio2c_iomux,
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GRF_GPIO2C0_SEL_MASK,
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GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
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rk_clrsetreg(&grf->gpio2c_iomux,
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GRF_GPIO2C1_SEL_MASK,
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GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
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#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1B0000)
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/* Enable early UART3 on the RK3399 */
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rk_clrsetreg(&grf->gpio3b_iomux,
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GRF_GPIO3B6_SEL_MASK,
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GRF_UART3_SIN << GRF_GPIO3B6_SEL_SHIFT);
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rk_clrsetreg(&grf->gpio3b_iomux,
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GRF_GPIO3B7_SEL_MASK,
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GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT);
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#else
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# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
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rk_setreg(&grf->io_vsel, 1 << 0);
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/*
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* Let's enable these power rails here, we are already running the SPI
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* Flash based code.
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*/
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spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */
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spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
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spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */
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spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
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#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
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/* Enable early UART2 channel C on the RK3399 */
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rk_clrsetreg(&grf->gpio4c_iomux,
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GRF_GPIO4C3_SEL_MASK,
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GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
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rk_clrsetreg(&grf->gpio4c_iomux,
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GRF_GPIO4C4_SEL_MASK,
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GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
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/* Set channel C as UART2 input */
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rk_clrsetreg(&grf->soc_con7,
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GRF_UART_DBG_SEL_MASK,
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GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
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#endif
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}
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#endif
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