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https://github.com/brain-hackers/u-boot-brain
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9ed303dfa9
This patch add base support for LX2162AQDS board. LX2162AQDS board supports LX2162A family SoCs. This patch add basic support of platform. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Signed-off-by: hui.song <hui.song_1@nxp.com> Signed-off-by: Manish Tomar <manish.tomar@nxp.com> Signed-off-by: Vikas Singh <vikas.singh@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
27 lines
518 B
Plaintext
27 lines
518 B
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 20
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*
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* Some assumptions are made:
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* * Mezzanine card M8 is connected to IO SLOT1
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* (xlaui4 for DPMAC 1)
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*
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* Copyright 2020 NXP
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*
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*/
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#include "fsl-lx2160a-qds.dtsi"
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&dpmac1 {
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status = "okay";
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phy-handle = <&cortina_phy1_0>;
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phy-connection-type = "xlaui4";
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};
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&emdio1_slot1 {
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cortina_phy1_0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x0>;
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};
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};
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