u-boot-brain/arch/riscv/lib
Leo Yu-Chi Liang 9ea6952a9a riscv: Fix efi header size for RV32
This patch depends on Atish's patch.
(https://patchwork.ozlabs.org/project/uboot/patch/20201013192331.3236458-1-atish.patra@wdc.com/)

Modify the size of the Optional Header "Windows-Specific Fields" to fit with the specification.
(https://docs.microsoft.com/en-us/windows/win32/debug/pe-format)

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Cc: rick@andestech.com
Cc: alankao@andestech.com
Cc: atish.patra@wdc.com
Cc: xypron.glpk@gmx.de
Cc: bmeng.cn@gmail.com
2020-12-14 15:16:54 +08:00
..
andes_plic.c riscv: Clean up initialization in Andes PLIC 2020-09-30 08:54:46 +08:00
asm-offsets.c riscv: Provide a mechanism to fix DT for reserved memory 2020-04-23 10:14:16 +08:00
boot.c command: Remove the cmd_tbl_t typedef 2020-05-18 18:36:55 -04:00
bootm.c common: Drop log.h from common header 2020-05-18 21:19:18 -04:00
cache.c common: Move some cache and MMU functions out of common.h 2019-12-02 18:23:55 -05:00
crt0_riscv_efi.S riscv: Fix efi header size for RV32 2020-12-14 15:16:54 +08:00
elf_riscv32_efi.lds SPDX: Convert single license tags to Linux Kernel style 2018-05-29 14:44:21 +08:00
elf_riscv64_efi.lds SPDX: Convert single license tags to Linux Kernel style 2018-05-29 14:44:21 +08:00
fdt_fixup.c fdtdec: optionally add property no-map to created reserved memory node 2020-09-22 12:54:13 -06:00
image.c common: Drop image.h from common header 2020-05-18 17:33:33 -04:00
interrupts.c riscv: reset after crash 2020-12-14 15:16:41 +08:00
Makefile riscv: Move Andes PLMT driver to drivers/timer 2020-10-26 10:01:28 +08:00
mkimage_fit_opensbi.sh riscv: add a generic FIT generator script 2019-08-26 16:07:42 +08:00
reloc_riscv_efi.c riscv: Remove unused _relocate arguments 2018-07-19 16:31:37 -04:00
reset.c Revert "riscv: Allow use of reset drivers" 2020-07-24 14:55:31 +08:00
sbi_ipi.c riscv: Clean up IPI initialization code 2020-07-01 15:01:22 +08:00
sbi.c cmd: provide command sbi 2020-08-25 09:34:47 +08:00
setjmp.S riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I 2018-11-26 13:57:29 +08:00
sifive_clint.c riscv: Move timer portions of SiFive CLINT to drivers/timer 2020-10-26 10:01:28 +08:00
smp.c riscv: Use a valid bit to ignore already-pending IPIs 2020-09-30 08:54:52 +08:00
spl.c riscv: fix building with CONFIG_SPL_SMP=n 2020-08-25 09:33:45 +08:00