mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-14 16:53:22 +09:00
fec4816387
The USB boot code is too fat and complicated to be included in SPL (at least for now). So, it was implemented as a separate project (what we call USB-loader). The expected boot sequence is as follows: Boot ROM -> USB-loader -> SPL -> U-Boot proper The USB-loader loads the SPL and U-Boot proper from a USB memory onto the locked L2 cache. Then, SPL needs to copy the U-Boot proper to DRAM, so this mode looks like a NOR boot from the view of SPL. However, we want to distinguish between (genuine) NOR boot and USB boot in some places. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
78 lines
2.8 KiB
C
78 lines
2.8 KiB
C
/*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <spl.h>
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#include <linux/io.h>
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#include "../sg-regs.h"
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#include "boot-device.h"
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static struct boot_device_info boot_device_table[] = {
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 4)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"},
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{BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 4)"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 4)"},
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{BOOT_DEVICE_SPI, "SPI 3Byte CS0"},
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{BOOT_DEVICE_SPI, "SPI 4Byte CS0"},
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{BOOT_DEVICE_SPI, "SPI 3Byte CS1"},
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{BOOT_DEVICE_SPI, "SPI 4Byte CS1"},
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{BOOT_DEVICE_SPI, "SPI 4Byte CS0"},
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{BOOT_DEVICE_SPI, "SPI 3Byte CS0"},
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{BOOT_DEVICE_NONE, "Reserved"},
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};
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static int get_boot_mode_sel(void)
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{
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return (readl(SG_PINMON0) >> 1) & 0x1f;
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}
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u32 proxstream2_boot_device(void)
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{
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int boot_mode;
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if (readl(SG_PINMON0) & BIT(6))
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return BOOT_DEVICE_USB;
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boot_mode = get_boot_mode_sel();
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return boot_device_table[boot_mode].type;
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}
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void proxstream2_boot_mode_show(void)
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{
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int mode_sel, i;
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mode_sel = get_boot_mode_sel();
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puts("Boot Mode Pin:\n");
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for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
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printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
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boot_device_table[i].info);
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}
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