mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
9e75875849
Add support for Freescale T4240 SoC. Feature of T4240 are
(incomplete list):
12 dual-threaded e6500 cores built on Power Architecture® technology
Arranged as clusters of four cores sharing a 2 MB L2 cache.
Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
v2.06-compliant)
Three levels of instruction: user, supervisor, and hypervisor
1.5 MB CoreNet Platform Cache (CPC)
Hierarchical interconnect fabric
CoreNet fabric supporting coherent and non-coherent transactions with
prioritization and bandwidth allocation amongst CoreNet end-points
1.6 Tbps coherent read bandwidth
Queue Manager (QMan) fabric supporting packet-level queue management and
quality of service scheduling
Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support
Memory prefetch engine (PMan)
Data Path Acceleration Architecture (DPAA) incorporating acceleration for
the following functions:
Packet parsing, classification, and distribution (Frame Manager 1.1)
Queue management for scheduling, packet sequencing, and congestion
management (Queue Manager 1.1)
Hardware buffer management for buffer allocation and de-allocation
(BMan 1.1)
Cryptography acceleration (SEC 5.0) at up to 40 Gbps
RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
32 SerDes lanes at up to 10.3125 GHz
Ethernet interfaces
Up to four 10 Gbps Ethernet MACs
Up to sixteen 1 Gbps Ethernet MACs
Maximum configuration of 4 x 10 GE + 8 x 1 GE
High-speed peripheral interfaces
Four PCI Express 2.0/3.0 controllers
Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
Type 11 messaging and Type 9 data streaming support
Interlaken look-aside interface for serial TCAM connection
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Four I2C controllers
Four 2-pin or two 4-pin UARTs
Integrated Flash controller supporting NAND and NOR flash
Two eight-channel DMA engines
Support for hardware virtualization and partitioning enforcement
QorIQ Platform's Trust Architecture 1.1
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
259 lines
6.1 KiB
C
259 lines
6.1 KiB
C
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/fsl_serdes.h>
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#include "fm.h"
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struct fm_eth_info fm_info[] = {
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#if (CONFIG_SYS_NUM_FM1_DTSEC >= 1)
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FM_DTSEC_INFO_INITIALIZER(1, 1),
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#endif
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#if (CONFIG_SYS_NUM_FM1_DTSEC >= 2)
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FM_DTSEC_INFO_INITIALIZER(1, 2),
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#endif
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#if (CONFIG_SYS_NUM_FM1_DTSEC >= 3)
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FM_DTSEC_INFO_INITIALIZER(1, 3),
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#endif
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#if (CONFIG_SYS_NUM_FM1_DTSEC >= 4)
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FM_DTSEC_INFO_INITIALIZER(1, 4),
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#endif
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#if (CONFIG_SYS_NUM_FM1_DTSEC >= 5)
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FM_DTSEC_INFO_INITIALIZER(1, 5),
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#endif
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#if (CONFIG_SYS_NUM_FM1_DTSEC >= 6)
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FM_DTSEC_INFO_INITIALIZER(1, 6),
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#endif
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#if (CONFIG_SYS_NUM_FM1_DTSEC >= 7)
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FM_DTSEC_INFO_INITIALIZER(1, 9),
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#endif
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#if (CONFIG_SYS_NUM_FM1_DTSEC >= 8)
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FM_DTSEC_INFO_INITIALIZER(1, 10),
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#endif
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#if (CONFIG_SYS_NUM_FM2_DTSEC >= 1)
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FM_DTSEC_INFO_INITIALIZER(2, 1),
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#endif
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#if (CONFIG_SYS_NUM_FM2_DTSEC >= 2)
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FM_DTSEC_INFO_INITIALIZER(2, 2),
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#endif
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#if (CONFIG_SYS_NUM_FM2_DTSEC >= 3)
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FM_DTSEC_INFO_INITIALIZER(2, 3),
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#endif
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#if (CONFIG_SYS_NUM_FM2_DTSEC >= 4)
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FM_DTSEC_INFO_INITIALIZER(2, 4),
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#endif
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#if (CONFIG_SYS_NUM_FM2_DTSEC >= 5)
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FM_DTSEC_INFO_INITIALIZER(2, 5),
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#endif
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#if (CONFIG_SYS_NUM_FM2_DTSEC >= 6)
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FM_DTSEC_INFO_INITIALIZER(2, 6),
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#endif
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#if (CONFIG_SYS_NUM_FM2_DTSEC >= 7)
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FM_DTSEC_INFO_INITIALIZER(2, 9),
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#endif
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#if (CONFIG_SYS_NUM_FM2_DTSEC >= 8)
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FM_DTSEC_INFO_INITIALIZER(2, 10),
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#endif
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#if (CONFIG_SYS_NUM_FM1_10GEC >= 1)
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FM_TGEC_INFO_INITIALIZER(1, 1),
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#endif
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#if (CONFIG_SYS_NUM_FM2_10GEC >= 1)
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FM_TGEC_INFO_INITIALIZER(2, 1),
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#endif
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};
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int fm_standard_init(bd_t *bis)
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{
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int i;
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struct ccsr_fman *reg;
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reg = (void *)CONFIG_SYS_FSL_FM1_ADDR;
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if (fm_init_common(0, reg))
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return 0;
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for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
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if ((fm_info[i].enabled) && (fm_info[i].index == 1))
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fm_eth_initialize(reg, &fm_info[i]);
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}
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#if (CONFIG_SYS_NUM_FMAN == 2)
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reg = (void *)CONFIG_SYS_FSL_FM2_ADDR;
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if (fm_init_common(1, reg))
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return 0;
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for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
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if ((fm_info[i].enabled) && (fm_info[i].index == 2))
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fm_eth_initialize(reg, &fm_info[i]);
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}
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#endif
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return 1;
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}
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/* simple linear search to map from port to array index */
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static int fm_port_to_index(enum fm_port port)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
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if (fm_info[i].port == port)
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return i;
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}
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return -1;
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}
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/*
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* Determine if an interface is actually active based on HW config
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* we expect fman_port_enet_if() to report PHY_INTERFACE_MODE_NONE if
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* the interface is not active based on HW cfg of the SoC
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*/
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void fman_enet_init(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
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phy_interface_t enet_if;
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enet_if = fman_port_enet_if(fm_info[i].port);
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if (enet_if != PHY_INTERFACE_MODE_NONE) {
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fm_info[i].enabled = 1;
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fm_info[i].enet_if = enet_if;
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} else {
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fm_info[i].enabled = 0;
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}
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}
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return ;
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}
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void fm_disable_port(enum fm_port port)
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{
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int i = fm_port_to_index(port);
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fm_info[i].enabled = 0;
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fman_disable_port(port);
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}
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void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus)
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{
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int i = fm_port_to_index(port);
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if (i == -1)
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return;
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fm_info[i].bus = bus;
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}
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void fm_info_set_phy_address(enum fm_port port, int address)
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{
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int i = fm_port_to_index(port);
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if (i == -1)
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return;
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fm_info[i].phy_addr = address;
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}
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/*
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* Returns the PHY address for a given Fman port
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*
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* The port must be set via a prior call to fm_info_set_phy_address().
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* A negative error code is returned if the port is invalid.
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*/
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int fm_info_get_phy_address(enum fm_port port)
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{
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int i = fm_port_to_index(port);
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if (i == -1)
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return -1;
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return fm_info[i].phy_addr;
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}
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/*
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* Returns the type of the data interface between the given MAC and its PHY.
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* This is typically determined by the RCW.
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*/
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phy_interface_t fm_info_get_enet_if(enum fm_port port)
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{
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int i = fm_port_to_index(port);
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if (i == -1)
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return PHY_INTERFACE_MODE_NONE;
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if (fm_info[i].enabled)
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return fm_info[i].enet_if;
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return PHY_INTERFACE_MODE_NONE;
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}
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static void
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__def_board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
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enum fm_port port, int offset)
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{
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return ;
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}
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void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
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enum fm_port port, int offset)
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__attribute__((weak, alias("__def_board_ft_fman_fixup_port")));
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static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
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{
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int off;
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uint32_t ph;
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phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset;
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u64 dtsec1_addr = (u64)CONFIG_SYS_CCSRBAR_PHYS +
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CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET;
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off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
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if (info->enabled) {
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fdt_fixup_phy_connection(blob, off, info->enet_if);
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board_ft_fman_fixup_port(blob, prop, paddr, info->port, off);
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return ;
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}
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/* board code might have caused offset to change */
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off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
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/* Don't disable FM1-DTSEC1 MAC as its used for MDIO */
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if (paddr != dtsec1_addr)
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fdt_status_disabled(blob, off); /* disable the MAC node */
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/* disable the fsl,dpa-ethernet node that points to the MAC */
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ph = fdt_get_phandle(blob, off);
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do_fixup_by_prop(blob, "fsl,fman-mac", &ph, sizeof(ph),
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"status", "disabled", strlen("disabled") + 1, 1);
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}
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void fdt_fixup_fman_ethernet(void *blob)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
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if (fm_info[i].type == FM_ETH_1G_E)
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ft_fixup_port(blob, &fm_info[i], "fsl,fman-1g-mac");
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else
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ft_fixup_port(blob, &fm_info[i], "fsl,fman-10g-mac");
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}
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}
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