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![Jagan Teki](/assets/img/avatar_default.png)
Add NAND support for Engicam i.CoreM6 qdl board. Boot Log: -------- U-Boot SPL 2016.09-rc2-30755-gd3dc581-dirty (Sep 28 2016 - 23:00:43) Trying to boot from NAND NAND : 512 MiB U-Boot 2016.09-rc2-30755-gd3dc581-dirty (Sep 28 2016 - 23:00:43 +0530) CPU: Freescale i.MX6SOLO rev1.3 at 792MHz CPU: Industrial temperature grade (-40C to 105C) at 55C Reset cause: WDOG Model: Engicam i.CoreM6 DualLite/Solo Starter Kit DRAM: 256 MiB NAND: 512 MiB MMC: FSL_SDHC: 0 In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 icorem6qdl> Cc: Scott Wood <oss@buserror.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
538 lines
13 KiB
C
538 lines
13 KiB
C
/*
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* Copyright (C) 2016 Amarula Solutions B.V.
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* Copyright (C) 2016 Engicam S.r.l.
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <linux/sizes.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/imx-common/iomux-v3.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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static iomux_v3_cfg_t const uart4_pads[] = {
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IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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};
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static iomux_v3_cfg_t const enet_pads[] = {
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IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL | PAD_CTL_SRE_FAST)),
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IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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};
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#ifdef CONFIG_FEC_MXC
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#define ENET_PHY_RST IMX_GPIO_NR(7, 12)
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static int setup_fec(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
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s32 timeout = 100000;
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u32 reg = 0;
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int ret;
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/* Enable fec clock */
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setbits_le32(&ccm->CCGR1, MXC_CCM_CCGR1_ENET_MASK);
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/* use 50MHz */
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ret = enable_fec_anatop_clock(0, ENET_50MHZ);
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if (ret)
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return ret;
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/* Enable PLLs */
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reg = readl(&anatop->pll_enet);
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reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
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writel(reg, &anatop->pll_enet);
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reg = readl(&anatop->pll_enet);
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reg |= BM_ANADIG_PLL_SYS_ENABLE;
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while (timeout--) {
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if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
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break;
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}
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if (timeout <= 0)
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return -EIO;
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reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
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writel(reg, &anatop->pll_enet);
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/* reset the phy */
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gpio_direction_output(ENET_PHY_RST, 0);
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udelay(10000);
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gpio_set_value(ENET_PHY_RST, 1);
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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int ret;
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SETUP_IOMUX_PADS(enet_pads);
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setup_fec();
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return ret = cpu_eth_init(bis);
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}
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#endif
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#ifdef CONFIG_NAND_MXS
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#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
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#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
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PAD_CTL_SRE_FAST)
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#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
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iomux_v3_cfg_t gpmi_pads[] = {
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IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
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IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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};
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static void setup_gpmi_nand(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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/* config gpmi nand iomux */
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SETUP_IOMUX_PADS(gpmi_pads);
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/* gate ENFC_CLK_ROOT clock first,before clk source switch */
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clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
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/* config gpmi and bch clock to 100 MHz */
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clrsetbits_le32(&mxc_ccm->cs2cdr,
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MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
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MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
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MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
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MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
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MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
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MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
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/* enable ENFC_CLK_ROOT clock */
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setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
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/* enable gpmi and bch clock gating */
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setbits_le32(&mxc_ccm->CCGR4,
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MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
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MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
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/* enable apbh clock gating */
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setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
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}
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#endif
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int board_early_init_f(void)
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{
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SETUP_IOMUX_PADS(uart4_pads);
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return 0;
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}
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int board_init(void)
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{
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/* Address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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#ifdef CONFIG_NAND_MXS
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setup_gpmi_nand();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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#include <libfdt.h>
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#include <spl.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/mx6-ddr.h>
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/* MMC board initialization is needed till adding DM support in SPL */
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#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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static iomux_v3_cfg_t const usdhc1_pads[] = {
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IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
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};
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#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
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struct fsl_esdhc_cfg usdhc_cfg[1] = {
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{USDHC1_BASE_ADDR, 0, 4},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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switch (cfg->esdhc_base) {
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case USDHC1_BASE_ADDR:
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ret = !gpio_get_value(USDHC1_CD_GPIO);
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break;
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}
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return ret;
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}
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int board_mmc_init(bd_t *bis)
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{
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int i, ret;
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/*
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* According to the board_mmc_init() the following map is done:
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* (U-boot device node) (Physical Port)
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* mmc0 USDHC1
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*/
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for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
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switch (i) {
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case 0:
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SETUP_IOMUX_PADS(usdhc1_pads);
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gpio_direction_input(USDHC1_CD_GPIO);
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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break;
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default:
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printf("Warning - USDHC%d controller not supporting\n",
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i + 1);
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return 0;
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}
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
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if (ret) {
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printf("Warning: failed to initialize mmc dev %d\n", i);
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return ret;
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}
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}
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return 0;
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}
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#endif
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/*
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* Driving strength:
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* 0x30 == 40 Ohm
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* 0x28 == 48 Ohm
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*/
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#define IMX6DQ_DRIVE_STRENGTH 0x30
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#define IMX6SDL_DRIVE_STRENGTH 0x28
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/* configure MX6Q/DUAL mmdc DDR io registers */
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static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
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.dram_sdqs0 = 0x28,
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.dram_sdqs1 = 0x28,
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.dram_sdqs2 = 0x28,
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.dram_sdqs3 = 0x28,
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.dram_sdqs4 = 0x28,
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.dram_sdqs5 = 0x28,
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.dram_sdqs6 = 0x28,
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.dram_sdqs7 = 0x28,
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.dram_dqm0 = 0x28,
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.dram_dqm1 = 0x28,
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.dram_dqm2 = 0x28,
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.dram_dqm3 = 0x28,
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.dram_dqm4 = 0x28,
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.dram_dqm5 = 0x28,
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.dram_dqm6 = 0x28,
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.dram_dqm7 = 0x28,
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.dram_cas = 0x30,
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.dram_ras = 0x30,
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.dram_sdclk_0 = 0x30,
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.dram_sdclk_1 = 0x30,
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.dram_reset = 0x30,
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.dram_sdcke0 = 0x3000,
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.dram_sdcke1 = 0x3000,
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.dram_sdba2 = 0x00000000,
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.dram_sdodt0 = 0x30,
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.dram_sdodt1 = 0x30,
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};
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/* configure MX6Q/DUAL mmdc GRP io registers */
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static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
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.grp_b0ds = 0x30,
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.grp_b1ds = 0x30,
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.grp_b2ds = 0x30,
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.grp_b3ds = 0x30,
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.grp_b4ds = 0x30,
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.grp_b5ds = 0x30,
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.grp_b6ds = 0x30,
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.grp_b7ds = 0x30,
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.grp_addds = 0x30,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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.grp_ddrmode = 0x00020000,
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.grp_ctlds = 0x30,
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.grp_ddr_type = 0x000c0000,
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};
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/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
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struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
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.dram_sdclk_0 = 0x30,
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.dram_sdclk_1 = 0x30,
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.dram_cas = 0x30,
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.dram_ras = 0x30,
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.dram_reset = 0x30,
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.dram_sdcke0 = 0x30,
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.dram_sdcke1 = 0x30,
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.dram_sdba2 = 0x00000000,
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.dram_sdodt0 = 0x30,
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.dram_sdodt1 = 0x30,
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.dram_sdqs0 = 0x28,
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.dram_sdqs1 = 0x28,
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.dram_sdqs2 = 0x28,
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.dram_sdqs3 = 0x28,
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.dram_sdqs4 = 0x28,
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.dram_sdqs5 = 0x28,
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.dram_sdqs6 = 0x28,
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.dram_sdqs7 = 0x28,
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.dram_dqm0 = 0x28,
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.dram_dqm1 = 0x28,
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.dram_dqm2 = 0x28,
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.dram_dqm3 = 0x28,
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.dram_dqm4 = 0x28,
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.dram_dqm5 = 0x28,
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.dram_dqm6 = 0x28,
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.dram_dqm7 = 0x28,
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};
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/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
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struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
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.grp_ddr_type = 0x000c0000,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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.grp_addds = 0x30,
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.grp_ctlds = 0x30,
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = 0x28,
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.grp_b1ds = 0x28,
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.grp_b2ds = 0x28,
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.grp_b3ds = 0x28,
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.grp_b4ds = 0x28,
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.grp_b5ds = 0x28,
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.grp_b6ds = 0x28,
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.grp_b7ds = 0x28,
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};
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/* mt41j256 */
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static struct mx6_ddr3_cfg mt41j256 = {
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.mem_speed = 1066,
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.density = 2,
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.width = 16,
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.banks = 8,
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.rowaddr = 13,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1375,
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.trcmin = 4875,
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.trasmin = 3500,
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.SRT = 0,
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};
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static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
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.p0_mpwldectrl0 = 0x000E0009,
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.p0_mpwldectrl1 = 0x0018000E,
|
|
.p1_mpwldectrl0 = 0x00000007,
|
|
.p1_mpwldectrl1 = 0x00000000,
|
|
.p0_mpdgctrl0 = 0x43280334,
|
|
.p0_mpdgctrl1 = 0x031C0314,
|
|
.p1_mpdgctrl0 = 0x4318031C,
|
|
.p1_mpdgctrl1 = 0x030C0258,
|
|
.p0_mprddlctl = 0x3E343A40,
|
|
.p1_mprddlctl = 0x383C3844,
|
|
.p0_mpwrdlctl = 0x40404440,
|
|
.p1_mpwrdlctl = 0x4C3E4446,
|
|
};
|
|
|
|
/* DDR 64bit */
|
|
static struct mx6_ddr_sysinfo mem_q = {
|
|
.ddr_type = DDR_TYPE_DDR3,
|
|
.dsize = 2,
|
|
.cs1_mirror = 0,
|
|
/* config for full 4GB range so that get_mem_size() works */
|
|
.cs_density = 32,
|
|
.ncs = 1,
|
|
.bi_on = 1,
|
|
.rtt_nom = 2,
|
|
.rtt_wr = 2,
|
|
.ralat = 5,
|
|
.walat = 0,
|
|
.mif3_mode = 3,
|
|
.rst_to_cke = 0x23,
|
|
.sde_to_rst = 0x10,
|
|
};
|
|
|
|
static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
|
|
.p0_mpwldectrl0 = 0x001F0024,
|
|
.p0_mpwldectrl1 = 0x00110018,
|
|
.p1_mpwldectrl0 = 0x001F0024,
|
|
.p1_mpwldectrl1 = 0x00110018,
|
|
.p0_mpdgctrl0 = 0x4230022C,
|
|
.p0_mpdgctrl1 = 0x02180220,
|
|
.p1_mpdgctrl0 = 0x42440248,
|
|
.p1_mpdgctrl1 = 0x02300238,
|
|
.p0_mprddlctl = 0x44444A48,
|
|
.p1_mprddlctl = 0x46484A42,
|
|
.p0_mpwrdlctl = 0x38383234,
|
|
.p1_mpwrdlctl = 0x3C34362E,
|
|
};
|
|
|
|
/* DDR 64bit 1GB */
|
|
static struct mx6_ddr_sysinfo mem_dl = {
|
|
.dsize = 2,
|
|
.cs1_mirror = 0,
|
|
/* config for full 4GB range so that get_mem_size() works */
|
|
.cs_density = 32,
|
|
.ncs = 1,
|
|
.bi_on = 1,
|
|
.rtt_nom = 1,
|
|
.rtt_wr = 1,
|
|
.ralat = 5,
|
|
.walat = 0,
|
|
.mif3_mode = 3,
|
|
.rst_to_cke = 0x23,
|
|
.sde_to_rst = 0x10,
|
|
};
|
|
|
|
/* DDR 32bit 512MB */
|
|
static struct mx6_ddr_sysinfo mem_s = {
|
|
.dsize = 1,
|
|
.cs1_mirror = 0,
|
|
/* config for full 4GB range so that get_mem_size() works */
|
|
.cs_density = 32,
|
|
.ncs = 1,
|
|
.bi_on = 1,
|
|
.rtt_nom = 1,
|
|
.rtt_wr = 1,
|
|
.ralat = 5,
|
|
.walat = 0,
|
|
.mif3_mode = 3,
|
|
.rst_to_cke = 0x23,
|
|
.sde_to_rst = 0x10,
|
|
};
|
|
|
|
static void ccgr_init(void)
|
|
{
|
|
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
|
|
|
writel(0x00003F3F, &ccm->CCGR0);
|
|
writel(0x0030FC00, &ccm->CCGR1);
|
|
writel(0x000FC000, &ccm->CCGR2);
|
|
writel(0x3F300000, &ccm->CCGR3);
|
|
writel(0xFF00F300, &ccm->CCGR4);
|
|
writel(0x0F0000C3, &ccm->CCGR5);
|
|
writel(0x000003CC, &ccm->CCGR6);
|
|
}
|
|
|
|
static void gpr_init(void)
|
|
{
|
|
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
|
|
|
/* enable AXI cache for VDOA/VPU/IPU */
|
|
writel(0xF00000CF, &iomux->gpr[4]);
|
|
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
|
|
writel(0x007F007F, &iomux->gpr[6]);
|
|
writel(0x007F007F, &iomux->gpr[7]);
|
|
}
|
|
|
|
static void spl_dram_init(void)
|
|
{
|
|
if (is_mx6solo()) {
|
|
mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
|
|
mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
|
|
} else if (is_mx6dl()) {
|
|
mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
|
|
mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
|
|
} else if (is_mx6dq()) {
|
|
mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
|
|
mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
|
|
}
|
|
|
|
udelay(100);
|
|
}
|
|
|
|
void board_init_f(ulong dummy)
|
|
{
|
|
ccgr_init();
|
|
|
|
/* setup AIPS and disable watchdog */
|
|
arch_cpu_init();
|
|
|
|
gpr_init();
|
|
|
|
/* iomux */
|
|
board_early_init_f();
|
|
|
|
/* setup GP timer */
|
|
timer_init();
|
|
|
|
/* UART clocks enabled and gd valid - init serial console */
|
|
preloader_console_init();
|
|
|
|
/* DDR initialization */
|
|
spl_dram_init();
|
|
|
|
/* Clear the BSS. */
|
|
memset(__bss_start, 0, __bss_end - __bss_start);
|
|
|
|
/* load/boot image from boot device */
|
|
board_init_r(NULL, 0);
|
|
}
|
|
#endif
|