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https://github.com/brain-hackers/u-boot-brain
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5ff8b35412
For files like the drivers/serial/serial.c, it must include the platform file, as the CONFIG_SYS_NS16550_COM1 must reference to the definition in the platform definition files. Include the platform definition file in the config file, so that it would decouple the dependence for the driver files. Signed-off-by: Lei Wen <leiwen@marvell.com>
72 lines
1.9 KiB
C
72 lines
1.9 KiB
C
/*
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* Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
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*
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* Based on original Kirkwood support which is
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/arch/cpu.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* orion5x_sdram_bar - reads SDRAM Base Address Register
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*/
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u32 orion5x_sdram_bar(enum memory_bank bank)
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{
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struct orion5x_ddr_addr_decode_registers *winregs =
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(struct orion5x_ddr_addr_decode_registers *)
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ORION5X_DRAM_BASE;
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u32 result = 0;
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u32 enable = 0x01 & winregs[bank].size;
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if ((!enable) || (bank > BANK3))
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return 0;
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result = winregs[bank].base;
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return result;
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}
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int dram_init (void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size(
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(long *) orion5x_sdram_bar(0),
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CONFIG_MAX_RAM_BANK_SIZE);
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return 0;
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}
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void dram_init_banksize (void)
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{
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int i;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
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gd->bd->bi_dram[i].size = get_ram_size(
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(long *) (gd->bd->bi_dram[i].start),
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CONFIG_MAX_RAM_BANK_SIZE);
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}
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}
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