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![Patrick Delaunay](/assets/img/avatar_default.png)
Allow fractional support in DDR tools. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
210 lines
3.7 KiB
C
210 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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#ifndef _RAM_STM32MP1_DDR_H
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#define _RAM_STM32MP1_DDR_H
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enum stm32mp1_ddr_interact_step {
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STEP_DDR_RESET,
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STEP_CTL_INIT,
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STEP_PHY_INIT,
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STEP_DDR_READY,
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STEP_RUN,
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};
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/* DDR CTL and DDR PHY REGISTERS */
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struct stm32mp1_ddrctl;
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struct stm32mp1_ddrphy;
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/**
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* struct ddr_info
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*
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* @dev: pointer for the device
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* @info: UCLASS RAM information
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* @ctl: DDR controleur base address
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* @clk: DDR clock
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* @phy: DDR PHY base address
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* @rcc: rcc base address
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*/
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struct ddr_info {
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struct udevice *dev;
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struct ram_info info;
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struct clk clk;
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struct stm32mp1_ddrctl *ctl;
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struct stm32mp1_ddrphy *phy;
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u32 rcc;
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};
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struct stm32mp1_ddrctrl_reg {
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u32 mstr;
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u32 mrctrl0;
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u32 mrctrl1;
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u32 derateen;
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u32 derateint;
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u32 pwrctl;
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u32 pwrtmg;
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u32 hwlpctl;
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u32 rfshctl0;
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u32 rfshctl3;
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u32 crcparctl0;
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u32 zqctl0;
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u32 dfitmg0;
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u32 dfitmg1;
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u32 dfilpcfg0;
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u32 dfiupd0;
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u32 dfiupd1;
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u32 dfiupd2;
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u32 dfiphymstr;
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u32 odtmap;
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u32 dbg0;
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u32 dbg1;
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u32 dbgcmd;
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u32 poisoncfg;
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u32 pccfg;
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};
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struct stm32mp1_ddrctrl_timing {
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u32 rfshtmg;
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u32 dramtmg0;
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u32 dramtmg1;
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u32 dramtmg2;
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u32 dramtmg3;
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u32 dramtmg4;
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u32 dramtmg5;
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u32 dramtmg6;
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u32 dramtmg7;
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u32 dramtmg8;
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u32 dramtmg14;
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u32 odtcfg;
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};
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struct stm32mp1_ddrctrl_map {
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u32 addrmap1;
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u32 addrmap2;
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u32 addrmap3;
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u32 addrmap4;
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u32 addrmap5;
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u32 addrmap6;
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u32 addrmap9;
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u32 addrmap10;
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u32 addrmap11;
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};
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struct stm32mp1_ddrctrl_perf {
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u32 sched;
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u32 sched1;
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u32 perfhpr1;
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u32 perflpr1;
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u32 perfwr1;
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u32 pcfgr_0;
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u32 pcfgw_0;
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u32 pcfgqos0_0;
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u32 pcfgqos1_0;
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u32 pcfgwqos0_0;
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u32 pcfgwqos1_0;
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u32 pcfgr_1;
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u32 pcfgw_1;
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u32 pcfgqos0_1;
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u32 pcfgqos1_1;
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u32 pcfgwqos0_1;
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u32 pcfgwqos1_1;
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};
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struct stm32mp1_ddrphy_reg {
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u32 pgcr;
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u32 aciocr;
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u32 dxccr;
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u32 dsgcr;
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u32 dcr;
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u32 odtcr;
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u32 zq0cr1;
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u32 dx0gcr;
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u32 dx1gcr;
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u32 dx2gcr;
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u32 dx3gcr;
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};
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struct stm32mp1_ddrphy_timing {
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u32 ptr0;
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u32 ptr1;
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u32 ptr2;
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u32 dtpr0;
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u32 dtpr1;
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u32 dtpr2;
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u32 mr0;
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u32 mr1;
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u32 mr2;
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u32 mr3;
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};
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struct stm32mp1_ddrphy_cal {
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u32 dx0dllcr;
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u32 dx0dqtr;
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u32 dx0dqstr;
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u32 dx1dllcr;
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u32 dx1dqtr;
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u32 dx1dqstr;
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u32 dx2dllcr;
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u32 dx2dqtr;
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u32 dx2dqstr;
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u32 dx3dllcr;
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u32 dx3dqtr;
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u32 dx3dqstr;
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};
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struct stm32mp1_ddr_info {
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const char *name;
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u32 speed; /* in kHZ */
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u32 size; /* memory size in byte = col * row * width */
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};
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struct stm32mp1_ddr_config {
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struct stm32mp1_ddr_info info;
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struct stm32mp1_ddrctrl_reg c_reg;
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struct stm32mp1_ddrctrl_timing c_timing;
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struct stm32mp1_ddrctrl_map c_map;
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struct stm32mp1_ddrctrl_perf c_perf;
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struct stm32mp1_ddrphy_reg p_reg;
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struct stm32mp1_ddrphy_timing p_timing;
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struct stm32mp1_ddrphy_cal p_cal;
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};
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int stm32mp1_ddr_clk_enable(struct ddr_info *priv, u32 mem_speed);
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void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir);
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void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl);
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void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
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u32 rfshctl3,
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u32 pwrctl);
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void stm32mp1_ddr_init(
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struct ddr_info *priv,
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const struct stm32mp1_ddr_config *config);
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int stm32mp1_dump_reg(const struct ddr_info *priv,
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const char *name);
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void stm32mp1_edit_reg(const struct ddr_info *priv,
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char *name,
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char *string);
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int stm32mp1_dump_param(const struct stm32mp1_ddr_config *config,
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const char *name);
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void stm32mp1_edit_param(const struct stm32mp1_ddr_config *config,
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char *name,
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char *string);
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void stm32mp1_dump_info(
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const struct ddr_info *priv,
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const struct stm32mp1_ddr_config *config);
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bool stm32mp1_ddr_interactive(
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void *priv,
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enum stm32mp1_ddr_interact_step step,
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const struct stm32mp1_ddr_config *config);
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#endif
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