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![Neil Armstrong](/assets/img/avatar_default.png)
The G12A PCIE PLL clock was introduced in Linux 5.2-rc1, and is needed for USB to operate, add basic support for it and associated gates. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
419 lines
9.9 KiB
C
419 lines
9.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
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* (C) Copyright 2018 - BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include <common.h>
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#include <asm/arch/clock-g12a.h>
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#include <asm/io.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <div64.h>
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#include <dt-bindings/clock/g12a-clkc.h>
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#include "clk_meson.h"
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#define XTAL_RATE 24000000
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struct meson_clk {
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struct regmap *map;
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};
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static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
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ulong rate, ulong current_rate);
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static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
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#define NUM_CLKS 178
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static struct meson_gate gates[NUM_CLKS] = {
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/* Everything Else (EE) domain gates */
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MESON_GATE(CLKID_SPICC0, HHI_GCLK_MPEG0, 8),
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MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9),
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MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13),
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MESON_GATE(CLKID_SPICC1, HHI_GCLK_MPEG0, 14),
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MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25),
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MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26),
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MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3),
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MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16),
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MESON_GATE(CLKID_USB, HHI_GCLK_MPEG1, 25),
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MESON_GATE(CLKID_USB1_DDR_BRIDGE, HHI_GCLK_MPEG2, 8),
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/* Peripheral Gates */
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MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23),
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MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7),
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};
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static int meson_set_gate(struct clk *clk, bool on)
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{
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struct meson_clk *priv = dev_get_priv(clk->dev);
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struct meson_gate *gate;
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if (clk->id >= ARRAY_SIZE(gates))
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return -ENOENT;
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gate = &gates[clk->id];
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if (gate->reg == 0)
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return 0;
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regmap_update_bits(priv->map, gate->reg,
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BIT(gate->bit), on ? BIT(gate->bit) : 0);
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return 0;
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}
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static int meson_clk_enable(struct clk *clk)
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{
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return meson_set_gate(clk, true);
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}
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static int meson_clk_disable(struct clk *clk)
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{
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return meson_set_gate(clk, false);
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}
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static unsigned long meson_clk81_get_rate(struct clk *clk)
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{
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struct meson_clk *priv = dev_get_priv(clk->dev);
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unsigned long parent_rate;
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uint reg;
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int parents[] = {
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-1,
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-1,
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CLKID_FCLK_DIV7,
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CLKID_MPLL1,
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CLKID_MPLL2,
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CLKID_FCLK_DIV4,
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CLKID_FCLK_DIV3,
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CLKID_FCLK_DIV5
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};
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/* mux */
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regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®);
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reg = (reg >> 12) & 7;
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switch (reg) {
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case 0:
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parent_rate = XTAL_RATE;
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break;
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case 1:
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return -ENOENT;
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default:
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parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]);
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}
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/* divider */
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regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®);
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reg = reg & ((1 << 7) - 1);
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return parent_rate / reg;
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}
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static long mpll_rate_from_params(unsigned long parent_rate,
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unsigned long sdm,
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unsigned long n2)
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{
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unsigned long divisor = (SDM_DEN * n2) + sdm;
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if (n2 < N2_MIN)
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return -EINVAL;
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return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
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}
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static struct parm meson_mpll0_parm[2] = {
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{HHI_MPLL_CNTL1, 0, 14}, /* psdm */
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{HHI_MPLL_CNTL1, 20, 9}, /* pn2 */
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};
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static struct parm meson_mpll1_parm[2] = {
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{HHI_MPLL_CNTL3, 0, 14}, /* psdm */
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{HHI_MPLL_CNTL3, 20, 9}, /* pn2 */
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};
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static struct parm meson_mpll2_parm[2] = {
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{HHI_MPLL_CNTL5, 0, 14}, /* psdm */
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{HHI_MPLL_CNTL5, 20, 9}, /* pn2 */
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};
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/*
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* MultiPhase Locked Loops are outputs from a PLL with additional frequency
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* scaling capabilities. MPLL rates are calculated as:
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*
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* f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
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*/
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static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
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{
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struct meson_clk *priv = dev_get_priv(clk->dev);
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struct parm *psdm, *pn2;
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unsigned long sdm, n2;
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unsigned long parent_rate;
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uint reg;
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switch (id) {
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case CLKID_MPLL0:
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psdm = &meson_mpll0_parm[0];
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pn2 = &meson_mpll0_parm[1];
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break;
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case CLKID_MPLL1:
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psdm = &meson_mpll1_parm[0];
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pn2 = &meson_mpll1_parm[1];
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break;
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case CLKID_MPLL2:
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psdm = &meson_mpll2_parm[0];
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pn2 = &meson_mpll2_parm[1];
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break;
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default:
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return -ENOENT;
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}
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parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL);
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if (IS_ERR_VALUE(parent_rate))
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return parent_rate;
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regmap_read(priv->map, psdm->reg_off, ®);
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sdm = PARM_GET(psdm->width, psdm->shift, reg);
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regmap_read(priv->map, pn2->reg_off, ®);
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n2 = PARM_GET(pn2->width, pn2->shift, reg);
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return mpll_rate_from_params(parent_rate, sdm, n2);
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}
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static struct parm meson_fixed_pll_parm[3] = {
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{HHI_FIX_PLL_CNTL0, 0, 8}, /* pm */
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{HHI_FIX_PLL_CNTL0, 10, 5}, /* pn */
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{HHI_FIX_PLL_CNTL0, 16, 2}, /* pod */
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};
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static struct parm meson_sys_pll_parm[3] = {
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{HHI_SYS_PLL_CNTL0, 0, 8}, /* pm */
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{HHI_SYS_PLL_CNTL0, 10, 5}, /* pn */
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{HHI_SYS_PLL_CNTL0, 16, 2}, /* pod */
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};
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static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
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{
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struct meson_clk *priv = dev_get_priv(clk->dev);
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struct parm *pm, *pn, *pod;
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unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
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u16 n, m, od;
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uint reg;
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/*
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* FIXME: Between the unit conversion and the missing frac, we know
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* rate will be slightly off ...
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*/
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switch (id) {
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case CLKID_FIXED_PLL:
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pm = &meson_fixed_pll_parm[0];
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pn = &meson_fixed_pll_parm[1];
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pod = &meson_fixed_pll_parm[2];
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break;
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case CLKID_SYS_PLL:
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pm = &meson_sys_pll_parm[0];
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pn = &meson_sys_pll_parm[1];
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pod = &meson_sys_pll_parm[2];
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break;
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default:
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return -ENOENT;
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}
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regmap_read(priv->map, pn->reg_off, ®);
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n = PARM_GET(pn->width, pn->shift, reg);
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regmap_read(priv->map, pm->reg_off, ®);
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m = PARM_GET(pm->width, pm->shift, reg);
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regmap_read(priv->map, pod->reg_off, ®);
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od = PARM_GET(pod->width, pod->shift, reg);
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return ((parent_rate_mhz * m / n) >> od) * 1000000;
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}
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static struct parm meson_pcie_pll_parm[3] = {
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{HHI_PCIE_PLL_CNTL0, 0, 8}, /* pm */
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{HHI_PCIE_PLL_CNTL0, 10, 5}, /* pn */
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{HHI_PCIE_PLL_CNTL0, 16, 5}, /* pod */
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};
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static ulong meson_pcie_pll_get_rate(struct clk *clk)
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{
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struct meson_clk *priv = dev_get_priv(clk->dev);
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struct parm *pm, *pn, *pod;
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unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
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u16 n, m, od;
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uint reg;
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pm = &meson_pcie_pll_parm[0];
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pn = &meson_pcie_pll_parm[1];
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pod = &meson_pcie_pll_parm[2];
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regmap_read(priv->map, pn->reg_off, ®);
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n = PARM_GET(pn->width, pn->shift, reg);
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regmap_read(priv->map, pm->reg_off, ®);
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m = PARM_GET(pm->width, pm->shift, reg);
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regmap_read(priv->map, pod->reg_off, ®);
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od = PARM_GET(pod->width, pod->shift, reg);
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return ((parent_rate_mhz * m / n) / 2 / od / 2) * 1000000;
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}
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static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
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{
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ulong rate;
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switch (id) {
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case CLKID_FIXED_PLL:
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case CLKID_SYS_PLL:
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rate = meson_pll_get_rate(clk, id);
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break;
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case CLKID_FCLK_DIV2:
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rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
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break;
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case CLKID_FCLK_DIV3:
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rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
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break;
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case CLKID_FCLK_DIV4:
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rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4;
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break;
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case CLKID_FCLK_DIV5:
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rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
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break;
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case CLKID_FCLK_DIV7:
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rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
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break;
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case CLKID_MPLL0:
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case CLKID_MPLL1:
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case CLKID_MPLL2:
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rate = meson_mpll_get_rate(clk, id);
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break;
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case CLKID_CLK81:
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rate = meson_clk81_get_rate(clk);
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break;
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case CLKID_PCIE_PLL:
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rate = meson_pcie_pll_get_rate(clk);
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break;
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default:
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if (gates[id].reg != 0) {
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/* a clock gate */
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rate = meson_clk81_get_rate(clk);
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break;
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}
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return -ENOENT;
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}
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debug("clock %lu has rate %lu\n", id, rate);
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return rate;
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}
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static ulong meson_clk_get_rate(struct clk *clk)
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{
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return meson_clk_get_rate_by_id(clk, clk->id);
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}
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static ulong meson_pcie_pll_set_rate(struct clk *clk, ulong rate)
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{
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struct meson_clk *priv = dev_get_priv(clk->dev);
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regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x20090496);
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regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x30090496);
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regmap_write(priv->map, HHI_PCIE_PLL_CNTL1, 0x00000000);
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regmap_write(priv->map, HHI_PCIE_PLL_CNTL2, 0x00001100);
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regmap_write(priv->map, HHI_PCIE_PLL_CNTL3, 0x10058e00);
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regmap_write(priv->map, HHI_PCIE_PLL_CNTL4, 0x000100c0);
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regmap_write(priv->map, HHI_PCIE_PLL_CNTL5, 0x68000048);
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regmap_write(priv->map, HHI_PCIE_PLL_CNTL5, 0x68000068);
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udelay(20);
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regmap_write(priv->map, HHI_PCIE_PLL_CNTL4, 0x008100c0);
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udelay(10);
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regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x34090496);
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regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x14090496);
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udelay(10);
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regmap_write(priv->map, HHI_PCIE_PLL_CNTL2, 0x00001000);
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regmap_update_bits(priv->map, HHI_PCIE_PLL_CNTL0,
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0x1f << 16, 9 << 16);
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return 100000000;
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}
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static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
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ulong rate, ulong current_rate)
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{
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if (current_rate == rate)
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return 0;
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switch (id) {
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/* Fixed clocks */
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case CLKID_PCIE_PLL:
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return meson_pcie_pll_set_rate(clk, rate);
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default:
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return -ENOENT;
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}
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return -EINVAL;
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}
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static ulong meson_clk_set_rate(struct clk *clk, ulong rate)
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{
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ulong current_rate = meson_clk_get_rate_by_id(clk, clk->id);
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int ret;
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if (IS_ERR_VALUE(current_rate))
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return current_rate;
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debug("%s: setting rate of %ld from %ld to %ld\n",
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__func__, clk->id, current_rate, rate);
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ret = meson_clk_set_rate_by_id(clk, clk->id, rate, current_rate);
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if (IS_ERR_VALUE(ret))
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return ret;
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debug("clock %lu has new rate %lu\n", clk->id,
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meson_clk_get_rate_by_id(clk, clk->id));
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return 0;
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}
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static int meson_clk_probe(struct udevice *dev)
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{
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struct meson_clk *priv = dev_get_priv(dev);
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priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node);
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if (IS_ERR(priv->map))
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return PTR_ERR(priv->map);
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debug("meson-clk-g12a: probed\n");
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return 0;
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}
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static struct clk_ops meson_clk_ops = {
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.disable = meson_clk_disable,
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.enable = meson_clk_enable,
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.get_rate = meson_clk_get_rate,
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.set_rate = meson_clk_set_rate,
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};
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static const struct udevice_id meson_clk_ids[] = {
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{ .compatible = "amlogic,g12a-clkc" },
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{ }
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};
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U_BOOT_DRIVER(meson_clk_g12a) = {
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.name = "meson_clk_g12a",
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.id = UCLASS_CLK,
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.of_match = meson_clk_ids,
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.priv_auto_alloc_size = sizeof(struct meson_clk),
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.ops = &meson_clk_ops,
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.probe = meson_clk_probe,
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};
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