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![Jagan Teki](/assets/img/avatar_default.png)
Add code to print the channel stride, this would help to print the stride of associated channel. Here is sample print on LPDDR4, 50MHz. 256B stride Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
148 lines
2.6 KiB
C
148 lines
2.6 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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* (C) Copyright 2019 Amarula Solutions.
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <common.h>
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#include <debug_uart.h>
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#include <asm/arch-rockchip/sdram_common.h>
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void sdram_print_dram_type(unsigned char dramtype)
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{
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switch (dramtype) {
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case DDR3:
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printascii("DDR3");
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break;
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case DDR4:
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printascii("DDR4");
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break;
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case LPDDR2:
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printascii("LPDDR2");
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break;
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case LPDDR3:
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printascii("LPDDR3");
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break;
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case LPDDR4:
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printascii("LPDDR4");
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break;
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default:
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printascii("Unknown Device");
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break;
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}
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}
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/**
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* cs = 0, cs0
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* cs = 1, cs1
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* cs => 2, cs0+cs1
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* note: it didn't consider about row_3_4
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*/
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u64 sdram_get_cs_cap(struct sdram_cap_info *cap_info, u32 cs, u32 dram_type)
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{
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u32 bg;
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u64 cap[2];
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if (dram_type == DDR4)
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/* DDR4 8bit dram BG = 2(4bank groups),
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* 16bit dram BG = 1 (2 bank groups)
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*/
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bg = (cap_info->dbw == 0) ? 2 : 1;
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else
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bg = 0;
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cap[0] = 1llu << (cap_info->bw + cap_info->col +
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bg + cap_info->bk + cap_info->cs0_row);
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if (cap_info->rank == 2)
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cap[1] = 1llu << (cap_info->bw + cap_info->col +
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bg + cap_info->bk + cap_info->cs1_row);
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else
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cap[1] = 0;
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if (cs == 0)
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return cap[0];
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else if (cs == 1)
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return cap[1];
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else
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return (cap[0] + cap[1]);
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}
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void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
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struct sdram_base_params *base)
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{
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u32 bg, cap;
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bg = (cap_info->dbw == 0) ? 2 : 1;
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sdram_print_dram_type(base->dramtype);
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printascii(", ");
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printdec(base->ddr_freq);
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printascii("MHz\n");
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printascii("BW=");
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printdec(8 << cap_info->bw);
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printascii(" Col=");
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printdec(cap_info->col);
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printascii(" Bk=");
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printdec(0x1 << cap_info->bk);
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if (base->dramtype == DDR4) {
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printascii(" BG=");
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printdec(1 << bg);
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}
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printascii(" CS0 Row=");
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printdec(cap_info->cs0_row);
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if (cap_info->rank > 1) {
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printascii(" CS1 Row=");
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printdec(cap_info->cs1_row);
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}
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printascii(" CS=");
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printdec(cap_info->rank);
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printascii(" Die BW=");
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printdec(8 << cap_info->dbw);
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cap = sdram_get_cs_cap(cap_info, 3, base->dramtype);
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if (cap_info->row_3_4)
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cap = cap * 3 / 4;
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printascii(" Size=");
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printdec(cap >> 20);
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printascii("MB\n");
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}
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void sdram_print_stride(unsigned int stride)
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{
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switch (stride) {
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case 0xc:
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printf("128B stride\n");
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break;
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case 5:
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case 9:
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case 0xd:
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case 0x11:
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case 0x19:
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printf("256B stride\n");
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break;
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case 0xa:
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case 0xe:
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case 0x12:
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printf("512B stride\n");
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break;
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case 0xf:
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printf("4K stride\n");
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break;
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case 0x1f:
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printf("32MB + 256B stride\n");
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break;
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default:
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printf("no stride\n");
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}
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}
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