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![Stefan Roese](/assets/img/avatar_default.png)
This patch adds a comment to explain the use of the hardcoded value for the number of address cells in mvebu_get_tgt_attr(). This should help to rework this function, once CONFIG_OF_LIVE is enabled for MVEBU in general. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
520 lines
14 KiB
C
520 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe driver for Marvell MVEBU SoCs
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*
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* Based on Barebox drivers/pci/pci-mvebu.c
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*
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* Ported to U-Boot by:
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* Anton Schubert <anton.schubert@gmx.de>
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* Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <dm/of_access.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <linux/errno.h>
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#include <linux/ioport.h>
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#include <linux/mbus.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* PCIe unit register offsets */
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#define SELECT(x, n) ((x >> n) & 1UL)
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#define PCIE_DEV_ID_OFF 0x0000
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#define PCIE_CMD_OFF 0x0004
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#define PCIE_DEV_REV_OFF 0x0008
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#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
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#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
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#define PCIE_CAPAB_OFF 0x0060
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#define PCIE_CTRL_STAT_OFF 0x0068
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#define PCIE_HEADER_LOG_4_OFF 0x0128
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#define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
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#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
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#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
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#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
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#define PCIE_WIN5_CTRL_OFF 0x1880
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#define PCIE_WIN5_BASE_OFF 0x1884
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#define PCIE_WIN5_REMAP_OFF 0x188c
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#define PCIE_CONF_ADDR_OFF 0x18f8
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#define PCIE_CONF_ADDR_EN BIT(31)
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#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
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#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
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#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
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#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
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#define PCIE_CONF_ADDR(dev, reg) \
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(PCIE_CONF_BUS(PCI_BUS(dev)) | PCIE_CONF_DEV(PCI_DEV(dev)) | \
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PCIE_CONF_FUNC(PCI_FUNC(dev)) | PCIE_CONF_REG(reg) | \
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PCIE_CONF_ADDR_EN)
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#define PCIE_CONF_DATA_OFF 0x18fc
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#define PCIE_MASK_OFF 0x1910
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#define PCIE_MASK_ENABLE_INTS (0xf << 24)
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#define PCIE_CTRL_OFF 0x1a00
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#define PCIE_CTRL_X1_MODE BIT(0)
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#define PCIE_STAT_OFF 0x1a04
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#define PCIE_STAT_BUS (0xff << 8)
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#define PCIE_STAT_DEV (0x1f << 16)
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#define PCIE_STAT_LINK_DOWN BIT(0)
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#define PCIE_DEBUG_CTRL 0x1a60
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#define PCIE_DEBUG_SOFT_RESET BIT(20)
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struct mvebu_pcie {
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struct pci_controller hose;
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void __iomem *base;
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void __iomem *membase;
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struct resource mem;
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void __iomem *iobase;
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u32 port;
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u32 lane;
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int devfn;
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u32 lane_mask;
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pci_dev_t dev;
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char name[16];
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unsigned int mem_target;
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unsigned int mem_attr;
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};
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/*
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* MVEBU PCIe controller needs MEMORY and I/O BARs to be mapped
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* into SoCs address space. Each controller will map 128M of MEM
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* and 64K of I/O space when registered.
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*/
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static void __iomem *mvebu_pcie_membase = (void __iomem *)MBUS_PCI_MEM_BASE;
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#define PCIE_MEM_SIZE (128 << 20)
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static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie)
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{
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u32 val;
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val = readl(pcie->base + PCIE_STAT_OFF);
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return !(val & PCIE_STAT_LINK_DOWN);
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}
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static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie *pcie, int busno)
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{
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u32 stat;
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stat = readl(pcie->base + PCIE_STAT_OFF);
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stat &= ~PCIE_STAT_BUS;
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stat |= busno << 8;
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writel(stat, pcie->base + PCIE_STAT_OFF);
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}
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static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie *pcie, int devno)
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{
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u32 stat;
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stat = readl(pcie->base + PCIE_STAT_OFF);
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stat &= ~PCIE_STAT_DEV;
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stat |= devno << 16;
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writel(stat, pcie->base + PCIE_STAT_OFF);
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}
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static int mvebu_pcie_get_local_bus_nr(struct mvebu_pcie *pcie)
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{
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u32 stat;
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stat = readl(pcie->base + PCIE_STAT_OFF);
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return (stat & PCIE_STAT_BUS) >> 8;
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}
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static int mvebu_pcie_get_local_dev_nr(struct mvebu_pcie *pcie)
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{
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u32 stat;
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stat = readl(pcie->base + PCIE_STAT_OFF);
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return (stat & PCIE_STAT_DEV) >> 16;
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}
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static inline struct mvebu_pcie *hose_to_pcie(struct pci_controller *hose)
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{
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return container_of(hose, struct mvebu_pcie, hose);
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}
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static int mvebu_pcie_read_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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struct mvebu_pcie *pcie = dev_get_platdata(bus);
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int local_bus = PCI_BUS(pcie->dev);
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int local_dev = PCI_DEV(pcie->dev);
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u32 reg;
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u32 data;
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debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
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/* Only allow one other device besides the local one on the local bus */
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if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) != local_dev) {
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if (local_dev == 0 && PCI_DEV(bdf) != 1) {
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debug("- out of range\n");
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/*
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* If local dev is 0, the first other dev can
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* only be 1
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*/
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*valuep = pci_get_ff(size);
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return 0;
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} else if (local_dev != 0 && PCI_DEV(bdf) != 0) {
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debug("- out of range\n");
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/*
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* If local dev is not 0, the first other dev can
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* only be 0
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*/
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*valuep = pci_get_ff(size);
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return 0;
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}
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}
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/* write address */
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reg = PCIE_CONF_ADDR(bdf, offset);
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writel(reg, pcie->base + PCIE_CONF_ADDR_OFF);
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data = readl(pcie->base + PCIE_CONF_DATA_OFF);
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debug("(addr,val)=(0x%04x, 0x%08x)\n", offset, data);
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*valuep = pci_conv_32_to_size(data, offset, size);
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return 0;
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}
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static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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struct mvebu_pcie *pcie = dev_get_platdata(bus);
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int local_bus = PCI_BUS(pcie->dev);
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int local_dev = PCI_DEV(pcie->dev);
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u32 data;
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debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
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debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
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/* Only allow one other device besides the local one on the local bus */
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if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) != local_dev) {
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if (local_dev == 0 && PCI_DEV(bdf) != 1) {
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/*
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* If local dev is 0, the first other dev can
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* only be 1
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*/
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return 0;
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} else if (local_dev != 0 && PCI_DEV(bdf) != 0) {
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/*
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* If local dev is not 0, the first other dev can
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* only be 0
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*/
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return 0;
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}
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}
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writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF);
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data = pci_conv_size_to_32(0, value, offset, size);
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writel(data, pcie->base + PCIE_CONF_DATA_OFF);
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return 0;
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}
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/*
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* Setup PCIE BARs and Address Decode Wins:
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* BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
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* WIN[0-3] -> DRAM bank[0-3]
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*/
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static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie)
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{
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const struct mbus_dram_target_info *dram = mvebu_mbus_dram_info();
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u32 size;
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int i;
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/* First, disable and clear BARs and windows. */
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for (i = 1; i < 3; i++) {
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writel(0, pcie->base + PCIE_BAR_CTRL_OFF(i));
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writel(0, pcie->base + PCIE_BAR_LO_OFF(i));
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writel(0, pcie->base + PCIE_BAR_HI_OFF(i));
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}
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for (i = 0; i < 5; i++) {
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writel(0, pcie->base + PCIE_WIN04_CTRL_OFF(i));
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writel(0, pcie->base + PCIE_WIN04_BASE_OFF(i));
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writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i));
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}
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writel(0, pcie->base + PCIE_WIN5_CTRL_OFF);
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writel(0, pcie->base + PCIE_WIN5_BASE_OFF);
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writel(0, pcie->base + PCIE_WIN5_REMAP_OFF);
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/* Setup windows for DDR banks. Count total DDR size on the fly. */
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size = 0;
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for (i = 0; i < dram->num_cs; i++) {
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const struct mbus_dram_window *cs = dram->cs + i;
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writel(cs->base & 0xffff0000,
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pcie->base + PCIE_WIN04_BASE_OFF(i));
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writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i));
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writel(((cs->size - 1) & 0xffff0000) |
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(cs->mbus_attr << 8) |
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(dram->mbus_dram_target_id << 4) | 1,
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pcie->base + PCIE_WIN04_CTRL_OFF(i));
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size += cs->size;
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}
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/* Round up 'size' to the nearest power of two. */
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if ((size & (size - 1)) != 0)
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size = 1 << fls(size);
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/* Setup BAR[1] to all DRAM banks. */
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writel(dram->cs[0].base | 0xc, pcie->base + PCIE_BAR_LO_OFF(1));
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writel(0, pcie->base + PCIE_BAR_HI_OFF(1));
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writel(((size - 1) & 0xffff0000) | 0x1,
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pcie->base + PCIE_BAR_CTRL_OFF(1));
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}
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static int mvebu_pcie_probe(struct udevice *dev)
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{
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struct mvebu_pcie *pcie = dev_get_platdata(dev);
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struct udevice *ctlr = pci_get_controller(dev);
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struct pci_controller *hose = dev_get_uclass_priv(ctlr);
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static int bus;
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u32 reg;
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debug("%s: PCIe %d.%d - up, base %08x\n", __func__,
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pcie->port, pcie->lane, (u32)pcie->base);
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/* Read Id info and local bus/dev */
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debug("direct conf read %08x, local bus %d, local dev %d\n",
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readl(pcie->base), mvebu_pcie_get_local_bus_nr(pcie),
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mvebu_pcie_get_local_dev_nr(pcie));
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mvebu_pcie_set_local_bus_nr(pcie, bus);
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mvebu_pcie_set_local_dev_nr(pcie, 0);
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pcie->dev = PCI_BDF(bus, 0, 0);
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pcie->mem.start = (u32)mvebu_pcie_membase;
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pcie->mem.end = pcie->mem.start + PCIE_MEM_SIZE - 1;
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mvebu_pcie_membase += PCIE_MEM_SIZE;
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if (mvebu_mbus_add_window_by_id(pcie->mem_target, pcie->mem_attr,
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(phys_addr_t)pcie->mem.start,
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PCIE_MEM_SIZE)) {
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printf("PCIe unable to add mbus window for mem at %08x+%08x\n",
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(u32)pcie->mem.start, PCIE_MEM_SIZE);
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}
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/* Setup windows and configure host bridge */
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mvebu_pcie_setup_wins(pcie);
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/* Master + slave enable. */
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reg = readl(pcie->base + PCIE_CMD_OFF);
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reg |= PCI_COMMAND_MEMORY;
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reg |= PCI_COMMAND_MASTER;
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reg |= BIT(10); /* disable interrupts */
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writel(reg, pcie->base + PCIE_CMD_OFF);
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/* Set BAR0 to internal registers */
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writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
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writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
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/* PCI memory space */
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pci_set_region(hose->regions + 0, pcie->mem.start,
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pcie->mem.start, PCIE_MEM_SIZE, PCI_REGION_MEM);
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pci_set_region(hose->regions + 1,
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0, 0,
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gd->ram_size,
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PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
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hose->region_count = 2;
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bus++;
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return 0;
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}
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static int mvebu_pcie_port_parse_dt(ofnode node, struct mvebu_pcie *pcie)
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{
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const u32 *addr;
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int len;
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addr = ofnode_get_property(node, "assigned-addresses", &len);
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if (!addr) {
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pr_err("property \"assigned-addresses\" not found");
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return -FDT_ERR_NOTFOUND;
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}
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pcie->base = (void *)(fdt32_to_cpu(addr[2]) + SOC_REGS_PHY_BASE);
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return 0;
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}
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#define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
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#define DT_TYPE_IO 0x1
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#define DT_TYPE_MEM32 0x2
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#define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
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#define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
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static int mvebu_get_tgt_attr(ofnode node, int devfn,
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unsigned long type,
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unsigned int *tgt,
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unsigned int *attr)
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{
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const int na = 3, ns = 2;
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const __be32 *range;
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int rlen, nranges, rangesz, pna, i;
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*tgt = -1;
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*attr = -1;
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range = ofnode_get_property(node, "ranges", &rlen);
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if (!range)
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return -EINVAL;
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/*
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* Linux uses of_n_addr_cells() to get the number of address cells
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* here. Currently this function is only available in U-Boot when
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* CONFIG_OF_LIVE is enabled. Until this is enabled for MVEBU in
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* general, lets't hardcode the "pna" value in the U-Boot code.
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*/
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pna = 2; /* hardcoded for now because of lack of of_n_addr_cells() */
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rangesz = pna + na + ns;
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nranges = rlen / sizeof(__be32) / rangesz;
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for (i = 0; i < nranges; i++, range += rangesz) {
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u32 flags = of_read_number(range, 1);
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u32 slot = of_read_number(range + 1, 1);
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u64 cpuaddr = of_read_number(range + na, pna);
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unsigned long rtype;
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if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
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rtype = IORESOURCE_IO;
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else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
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rtype = IORESOURCE_MEM;
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else
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continue;
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/*
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* The Linux code used PCI_SLOT() here, which expects devfn
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* in bits 7..0. PCI_DEV() in U-Boot is similar to PCI_SLOT(),
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* only expects devfn in 15..8, where its saved in this driver.
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*/
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if (slot == PCI_DEV(devfn) && type == rtype) {
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*tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
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*attr = DT_CPUADDR_TO_ATTR(cpuaddr);
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return 0;
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}
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}
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return -ENOENT;
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}
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static int mvebu_pcie_ofdata_to_platdata(struct udevice *dev)
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{
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struct mvebu_pcie *pcie = dev_get_platdata(dev);
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int ret = 0;
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/* Get port number, lane number and memory target / attr */
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if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-port",
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&pcie->port)) {
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ret = -ENODEV;
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goto err;
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}
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if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-lane", &pcie->lane))
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pcie->lane = 0;
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sprintf(pcie->name, "pcie%d.%d", pcie->port, pcie->lane);
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/* pci_get_devfn() returns devfn in bits 15..8, see PCI_DEV usage */
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pcie->devfn = pci_get_devfn(dev);
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if (pcie->devfn < 0) {
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ret = -ENODEV;
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goto err;
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}
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ret = mvebu_get_tgt_attr(dev_ofnode(dev->parent), pcie->devfn,
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IORESOURCE_MEM,
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&pcie->mem_target, &pcie->mem_attr);
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if (ret < 0) {
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printf("%s: cannot get tgt/attr for mem window\n", pcie->name);
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goto err;
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}
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|
/* Parse PCIe controller register base from DT */
|
|
ret = mvebu_pcie_port_parse_dt(dev_ofnode(dev), pcie);
|
|
if (ret < 0)
|
|
goto err;
|
|
|
|
/* Check link and skip ports that have no link */
|
|
if (!mvebu_pcie_link_up(pcie)) {
|
|
debug("%s: %s - down\n", __func__, pcie->name);
|
|
ret = -ENODEV;
|
|
goto err;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
static const struct dm_pci_ops mvebu_pcie_ops = {
|
|
.read_config = mvebu_pcie_read_config,
|
|
.write_config = mvebu_pcie_write_config,
|
|
};
|
|
|
|
static struct driver pcie_mvebu_drv = {
|
|
.name = "pcie_mvebu",
|
|
.id = UCLASS_PCI,
|
|
.ops = &mvebu_pcie_ops,
|
|
.probe = mvebu_pcie_probe,
|
|
.ofdata_to_platdata = mvebu_pcie_ofdata_to_platdata,
|
|
.platdata_auto_alloc_size = sizeof(struct mvebu_pcie),
|
|
};
|
|
|
|
/*
|
|
* Use a MISC device to bind the n instances (child nodes) of the
|
|
* PCIe base controller in UCLASS_PCI.
|
|
*/
|
|
static int mvebu_pcie_bind(struct udevice *parent)
|
|
{
|
|
struct mvebu_pcie *pcie;
|
|
struct uclass_driver *drv;
|
|
struct udevice *dev;
|
|
ofnode subnode;
|
|
|
|
/* Lookup eth driver */
|
|
drv = lists_uclass_lookup(UCLASS_PCI);
|
|
if (!drv) {
|
|
puts("Cannot find PCI driver\n");
|
|
return -ENOENT;
|
|
}
|
|
|
|
ofnode_for_each_subnode(subnode, dev_ofnode(parent)) {
|
|
if (!ofnode_is_available(subnode))
|
|
continue;
|
|
|
|
pcie = calloc(1, sizeof(*pcie));
|
|
if (!pcie)
|
|
return -ENOMEM;
|
|
|
|
/* Create child device UCLASS_PCI and bind it */
|
|
device_bind_ofnode(parent, &pcie_mvebu_drv, pcie->name, pcie,
|
|
subnode, &dev);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id mvebu_pcie_ids[] = {
|
|
{ .compatible = "marvell,armada-xp-pcie" },
|
|
{ .compatible = "marvell,armada-370-pcie" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(pcie_mvebu_base) = {
|
|
.name = "pcie_mvebu_base",
|
|
.id = UCLASS_MISC,
|
|
.of_match = mvebu_pcie_ids,
|
|
.bind = mvebu_pcie_bind,
|
|
};
|