mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-14 22:23:56 +09:00
![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
972 lines
24 KiB
C
972 lines
24 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2014-2017 Broadcom.
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*/
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#ifdef BCM_GMAC_DEBUG
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#ifndef DEBUG
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#define DEBUG
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#endif
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#endif
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#include <config.h>
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#include <common.h>
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#include <malloc.h>
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#include <net.h>
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#include <asm/io.h>
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#include <phy.h>
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#include "bcm-sf2-eth.h"
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#include "bcm-sf2-eth-gmac.h"
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#define SPINWAIT(exp, us) { \
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uint countdown = (us) + 9; \
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while ((exp) && (countdown >= 10)) {\
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udelay(10); \
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countdown -= 10; \
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} \
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}
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#define RX_BUF_SIZE_ALIGNED ALIGN(RX_BUF_SIZE, ARCH_DMA_MINALIGN)
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#define TX_BUF_SIZE_ALIGNED ALIGN(TX_BUF_SIZE, ARCH_DMA_MINALIGN)
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#define DESCP_SIZE_ALIGNED ALIGN(sizeof(dma64dd_t), ARCH_DMA_MINALIGN)
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static int gmac_disable_dma(struct eth_dma *dma, int dir);
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static int gmac_enable_dma(struct eth_dma *dma, int dir);
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/* DMA Descriptor */
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typedef struct {
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/* misc control bits */
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uint32_t ctrl1;
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/* buffer count and address extension */
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uint32_t ctrl2;
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/* memory address of the date buffer, bits 31:0 */
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uint32_t addrlow;
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/* memory address of the date buffer, bits 63:32 */
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uint32_t addrhigh;
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} dma64dd_t;
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uint32_t g_dmactrlflags;
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static uint32_t dma_ctrlflags(uint32_t mask, uint32_t flags)
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{
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debug("%s enter\n", __func__);
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g_dmactrlflags &= ~mask;
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g_dmactrlflags |= flags;
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/* If trying to enable parity, check if parity is actually supported */
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if (g_dmactrlflags & DMA_CTRL_PEN) {
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uint32_t control;
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control = readl(GMAC0_DMA_TX_CTRL_ADDR);
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writel(control | D64_XC_PD, GMAC0_DMA_TX_CTRL_ADDR);
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if (readl(GMAC0_DMA_TX_CTRL_ADDR) & D64_XC_PD) {
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/*
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* We *can* disable it, therefore it is supported;
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* restore control register
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*/
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writel(control, GMAC0_DMA_TX_CTRL_ADDR);
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} else {
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/* Not supported, don't allow it to be enabled */
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g_dmactrlflags &= ~DMA_CTRL_PEN;
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}
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}
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return g_dmactrlflags;
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}
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static inline void reg32_clear_bits(uint32_t reg, uint32_t value)
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{
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uint32_t v = readl(reg);
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v &= ~(value);
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writel(v, reg);
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}
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static inline void reg32_set_bits(uint32_t reg, uint32_t value)
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{
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uint32_t v = readl(reg);
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v |= value;
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writel(v, reg);
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}
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#ifdef BCM_GMAC_DEBUG
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static void dma_tx_dump(struct eth_dma *dma)
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{
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dma64dd_t *descp = NULL;
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uint8_t *bufp;
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int i;
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printf("TX DMA Register:\n");
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printf("control:0x%x; ptr:0x%x; addrl:0x%x; addrh:0x%x; stat0:0x%x, stat1:0x%x\n",
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readl(GMAC0_DMA_TX_CTRL_ADDR),
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readl(GMAC0_DMA_TX_PTR_ADDR),
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readl(GMAC0_DMA_TX_ADDR_LOW_ADDR),
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readl(GMAC0_DMA_TX_ADDR_HIGH_ADDR),
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readl(GMAC0_DMA_TX_STATUS0_ADDR),
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readl(GMAC0_DMA_TX_STATUS1_ADDR));
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printf("TX Descriptors:\n");
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for (i = 0; i < TX_BUF_NUM; i++) {
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descp = (dma64dd_t *)(dma->tx_desc_aligned) + i;
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printf("ctrl1:0x%08x; ctrl2:0x%08x; addr:0x%x 0x%08x\n",
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descp->ctrl1, descp->ctrl2,
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descp->addrhigh, descp->addrlow);
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}
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printf("TX Buffers:\n");
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/* Initialize TX DMA descriptor table */
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for (i = 0; i < TX_BUF_NUM; i++) {
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bufp = (uint8_t *)(dma->tx_buf + i * TX_BUF_SIZE_ALIGNED);
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printf("buf%d:0x%x; ", i, (uint32_t)bufp);
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}
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printf("\n");
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}
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static void dma_rx_dump(struct eth_dma *dma)
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{
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dma64dd_t *descp = NULL;
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uint8_t *bufp;
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int i;
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printf("RX DMA Register:\n");
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printf("control:0x%x; ptr:0x%x; addrl:0x%x; addrh:0x%x; stat0:0x%x, stat1:0x%x\n",
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readl(GMAC0_DMA_RX_CTRL_ADDR),
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readl(GMAC0_DMA_RX_PTR_ADDR),
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readl(GMAC0_DMA_RX_ADDR_LOW_ADDR),
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readl(GMAC0_DMA_RX_ADDR_HIGH_ADDR),
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readl(GMAC0_DMA_RX_STATUS0_ADDR),
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readl(GMAC0_DMA_RX_STATUS1_ADDR));
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printf("RX Descriptors:\n");
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for (i = 0; i < RX_BUF_NUM; i++) {
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descp = (dma64dd_t *)(dma->rx_desc_aligned) + i;
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printf("ctrl1:0x%08x; ctrl2:0x%08x; addr:0x%x 0x%08x\n",
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descp->ctrl1, descp->ctrl2,
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descp->addrhigh, descp->addrlow);
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}
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printf("RX Buffers:\n");
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for (i = 0; i < RX_BUF_NUM; i++) {
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bufp = dma->rx_buf + i * RX_BUF_SIZE_ALIGNED;
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printf("buf%d:0x%x; ", i, (uint32_t)bufp);
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}
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printf("\n");
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}
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#endif
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static int dma_tx_init(struct eth_dma *dma)
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{
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dma64dd_t *descp = NULL;
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uint8_t *bufp;
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int i;
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uint32_t ctrl;
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debug("%s enter\n", __func__);
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/* clear descriptor memory */
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memset((void *)(dma->tx_desc_aligned), 0,
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TX_BUF_NUM * DESCP_SIZE_ALIGNED);
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memset(dma->tx_buf, 0, TX_BUF_NUM * TX_BUF_SIZE_ALIGNED);
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/* Initialize TX DMA descriptor table */
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for (i = 0; i < TX_BUF_NUM; i++) {
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descp = (dma64dd_t *)(dma->tx_desc_aligned) + i;
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bufp = dma->tx_buf + i * TX_BUF_SIZE_ALIGNED;
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/* clear buffer memory */
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memset((void *)bufp, 0, TX_BUF_SIZE_ALIGNED);
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ctrl = 0;
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/* if last descr set endOfTable */
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if (i == (TX_BUF_NUM-1))
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ctrl = D64_CTRL1_EOT;
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descp->ctrl1 = ctrl;
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descp->ctrl2 = 0;
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descp->addrlow = (uint32_t)bufp;
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descp->addrhigh = 0;
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}
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/* flush descriptor and buffer */
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descp = dma->tx_desc_aligned;
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bufp = dma->tx_buf;
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flush_dcache_range((unsigned long)descp,
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(unsigned long)descp +
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DESCP_SIZE_ALIGNED * TX_BUF_NUM);
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flush_dcache_range((unsigned long)bufp,
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(unsigned long)bufp +
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TX_BUF_SIZE_ALIGNED * TX_BUF_NUM);
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/* initialize the DMA channel */
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writel((uint32_t)(dma->tx_desc_aligned), GMAC0_DMA_TX_ADDR_LOW_ADDR);
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writel(0, GMAC0_DMA_TX_ADDR_HIGH_ADDR);
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/* now update the dma last descriptor */
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writel(((uint32_t)(dma->tx_desc_aligned)) & D64_XP_LD_MASK,
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GMAC0_DMA_TX_PTR_ADDR);
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return 0;
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}
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static int dma_rx_init(struct eth_dma *dma)
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{
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uint32_t last_desc;
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dma64dd_t *descp = NULL;
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uint8_t *bufp;
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uint32_t ctrl;
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int i;
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debug("%s enter\n", __func__);
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/* clear descriptor memory */
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memset((void *)(dma->rx_desc_aligned), 0,
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RX_BUF_NUM * DESCP_SIZE_ALIGNED);
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/* clear buffer memory */
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memset(dma->rx_buf, 0, RX_BUF_NUM * RX_BUF_SIZE_ALIGNED);
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/* Initialize RX DMA descriptor table */
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for (i = 0; i < RX_BUF_NUM; i++) {
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descp = (dma64dd_t *)(dma->rx_desc_aligned) + i;
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bufp = dma->rx_buf + i * RX_BUF_SIZE_ALIGNED;
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ctrl = 0;
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/* if last descr set endOfTable */
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if (i == (RX_BUF_NUM - 1))
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ctrl = D64_CTRL1_EOT;
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descp->ctrl1 = ctrl;
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descp->ctrl2 = RX_BUF_SIZE_ALIGNED;
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descp->addrlow = (uint32_t)bufp;
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descp->addrhigh = 0;
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last_desc = ((uint32_t)(descp) & D64_XP_LD_MASK)
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+ sizeof(dma64dd_t);
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}
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descp = dma->rx_desc_aligned;
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bufp = dma->rx_buf;
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/* flush descriptor and buffer */
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flush_dcache_range((unsigned long)descp,
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(unsigned long)descp +
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DESCP_SIZE_ALIGNED * RX_BUF_NUM);
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flush_dcache_range((unsigned long)(bufp),
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(unsigned long)bufp +
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RX_BUF_SIZE_ALIGNED * RX_BUF_NUM);
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/* initailize the DMA channel */
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writel((uint32_t)descp, GMAC0_DMA_RX_ADDR_LOW_ADDR);
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writel(0, GMAC0_DMA_RX_ADDR_HIGH_ADDR);
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/* now update the dma last descriptor */
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writel(last_desc, GMAC0_DMA_RX_PTR_ADDR);
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return 0;
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}
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static int dma_init(struct eth_dma *dma)
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{
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debug(" %s enter\n", __func__);
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/*
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* Default flags: For backwards compatibility both
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* Rx Overflow Continue and Parity are DISABLED.
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*/
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dma_ctrlflags(DMA_CTRL_ROC | DMA_CTRL_PEN, 0);
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debug("rx burst len 0x%x\n",
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(readl(GMAC0_DMA_RX_CTRL_ADDR) & D64_RC_BL_MASK)
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>> D64_RC_BL_SHIFT);
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debug("tx burst len 0x%x\n",
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(readl(GMAC0_DMA_TX_CTRL_ADDR) & D64_XC_BL_MASK)
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>> D64_XC_BL_SHIFT);
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dma_tx_init(dma);
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dma_rx_init(dma);
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/* From end of chip_init() */
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/* enable the overflow continue feature and disable parity */
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dma_ctrlflags(DMA_CTRL_ROC | DMA_CTRL_PEN /* mask */,
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DMA_CTRL_ROC /* value */);
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return 0;
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}
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static int dma_deinit(struct eth_dma *dma)
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{
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debug(" %s enter\n", __func__);
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gmac_disable_dma(dma, MAC_DMA_RX);
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gmac_disable_dma(dma, MAC_DMA_TX);
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free(dma->tx_buf);
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dma->tx_buf = NULL;
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free(dma->tx_desc_aligned);
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dma->tx_desc_aligned = NULL;
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free(dma->rx_buf);
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dma->rx_buf = NULL;
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free(dma->rx_desc_aligned);
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dma->rx_desc_aligned = NULL;
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return 0;
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}
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int gmac_tx_packet(struct eth_dma *dma, void *packet, int length)
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{
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uint8_t *bufp = dma->tx_buf + dma->cur_tx_index * TX_BUF_SIZE_ALIGNED;
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/* kick off the dma */
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size_t len = length;
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int txout = dma->cur_tx_index;
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uint32_t flags;
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dma64dd_t *descp = NULL;
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uint32_t ctrl;
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uint32_t last_desc = (((uint32_t)dma->tx_desc_aligned) +
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sizeof(dma64dd_t)) & D64_XP_LD_MASK;
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size_t buflen;
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debug("%s enter\n", __func__);
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/* load the buffer */
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memcpy(bufp, packet, len);
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/* Add 4 bytes for Ethernet FCS/CRC */
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buflen = len + 4;
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ctrl = (buflen & D64_CTRL2_BC_MASK);
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/* the transmit will only be one frame or set SOF, EOF */
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/* also set int on completion */
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flags = D64_CTRL1_SOF | D64_CTRL1_IOC | D64_CTRL1_EOF;
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/* txout points to the descriptor to uset */
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/* if last descriptor then set EOT */
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if (txout == (TX_BUF_NUM - 1)) {
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flags |= D64_CTRL1_EOT;
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last_desc = ((uint32_t)(dma->tx_desc_aligned)) & D64_XP_LD_MASK;
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}
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/* write the descriptor */
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descp = ((dma64dd_t *)(dma->tx_desc_aligned)) + txout;
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descp->addrlow = (uint32_t)bufp;
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descp->addrhigh = 0;
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descp->ctrl1 = flags;
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descp->ctrl2 = ctrl;
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/* flush descriptor and buffer */
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flush_dcache_range((unsigned long)dma->tx_desc_aligned,
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(unsigned long)dma->tx_desc_aligned +
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DESCP_SIZE_ALIGNED * TX_BUF_NUM);
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flush_dcache_range((unsigned long)bufp,
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(unsigned long)bufp + TX_BUF_SIZE_ALIGNED);
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/* now update the dma last descriptor */
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writel(last_desc, GMAC0_DMA_TX_PTR_ADDR);
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/* tx dma should be enabled so packet should go out */
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/* update txout */
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dma->cur_tx_index = (txout + 1) & (TX_BUF_NUM - 1);
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return 0;
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}
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bool gmac_check_tx_done(struct eth_dma *dma)
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{
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/* wait for tx to complete */
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uint32_t intstatus;
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bool xfrdone = false;
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debug("%s enter\n", __func__);
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intstatus = readl(GMAC0_INT_STATUS_ADDR);
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debug("int(0x%x)\n", intstatus);
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if (intstatus & (I_XI0 | I_XI1 | I_XI2 | I_XI3)) {
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xfrdone = true;
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/* clear the int bits */
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intstatus &= ~(I_XI0 | I_XI1 | I_XI2 | I_XI3);
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writel(intstatus, GMAC0_INT_STATUS_ADDR);
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} else {
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debug("Tx int(0x%x)\n", intstatus);
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}
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return xfrdone;
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}
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int gmac_check_rx_done(struct eth_dma *dma, uint8_t *buf)
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{
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void *bufp, *datap;
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size_t rcvlen = 0, buflen = 0;
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uint32_t stat0 = 0, stat1 = 0;
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uint32_t control, offset;
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uint8_t statbuf[HWRXOFF*2];
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int index, curr, active;
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dma64dd_t *descp = NULL;
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/* udelay(50); */
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/*
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* this api will check if a packet has been received.
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* If so it will return the address of the buffer and current
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* descriptor index will be incremented to the
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* next descriptor. Once done with the frame the buffer should be
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* added back onto the descriptor and the lastdscr should be updated
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* to this descriptor.
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*/
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index = dma->cur_rx_index;
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offset = (uint32_t)(dma->rx_desc_aligned);
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stat0 = readl(GMAC0_DMA_RX_STATUS0_ADDR) & D64_RS0_CD_MASK;
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stat1 = readl(GMAC0_DMA_RX_STATUS1_ADDR) & D64_RS0_CD_MASK;
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curr = ((stat0 - offset) & D64_RS0_CD_MASK) / sizeof(dma64dd_t);
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active = ((stat1 - offset) & D64_RS0_CD_MASK) / sizeof(dma64dd_t);
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/* check if any frame */
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if (index == curr)
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return -1;
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debug("received packet\n");
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debug("expect(0x%x) curr(0x%x) active(0x%x)\n", index, curr, active);
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/* remove warning */
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if (index == active)
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;
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/* get the packet pointer that corresponds to the rx descriptor */
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bufp = dma->rx_buf + index * RX_BUF_SIZE_ALIGNED;
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descp = (dma64dd_t *)(dma->rx_desc_aligned) + index;
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/* flush descriptor and buffer */
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flush_dcache_range((unsigned long)dma->rx_desc_aligned,
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(unsigned long)dma->rx_desc_aligned +
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DESCP_SIZE_ALIGNED * RX_BUF_NUM);
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flush_dcache_range((unsigned long)bufp,
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(unsigned long)bufp + RX_BUF_SIZE_ALIGNED);
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buflen = (descp->ctrl2 & D64_CTRL2_BC_MASK);
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stat0 = readl(GMAC0_DMA_RX_STATUS0_ADDR);
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stat1 = readl(GMAC0_DMA_RX_STATUS1_ADDR);
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debug("bufp(0x%x) index(0x%x) buflen(0x%x) stat0(0x%x) stat1(0x%x)\n",
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(uint32_t)bufp, index, buflen, stat0, stat1);
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dma->cur_rx_index = (index + 1) & (RX_BUF_NUM - 1);
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/* get buffer offset */
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control = readl(GMAC0_DMA_RX_CTRL_ADDR);
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offset = (control & D64_RC_RO_MASK) >> D64_RC_RO_SHIFT;
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rcvlen = *(uint16_t *)bufp;
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debug("Received %d bytes\n", rcvlen);
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/* copy status into temp buf then copy data from rx buffer */
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memcpy(statbuf, bufp, offset);
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datap = (void *)((uint32_t)bufp + offset);
|
|
memcpy(buf, datap, rcvlen);
|
|
|
|
/* update descriptor that is being added back on ring */
|
|
descp->ctrl2 = RX_BUF_SIZE_ALIGNED;
|
|
descp->addrlow = (uint32_t)bufp;
|
|
descp->addrhigh = 0;
|
|
/* flush descriptor */
|
|
flush_dcache_range((unsigned long)dma->rx_desc_aligned,
|
|
(unsigned long)dma->rx_desc_aligned +
|
|
DESCP_SIZE_ALIGNED * RX_BUF_NUM);
|
|
|
|
/* set the lastdscr for the rx ring */
|
|
writel(((uint32_t)descp) & D64_XP_LD_MASK, GMAC0_DMA_RX_PTR_ADDR);
|
|
|
|
return (int)rcvlen;
|
|
}
|
|
|
|
static int gmac_disable_dma(struct eth_dma *dma, int dir)
|
|
{
|
|
int status;
|
|
|
|
debug("%s enter\n", __func__);
|
|
|
|
if (dir == MAC_DMA_TX) {
|
|
/* address PR8249/PR7577 issue */
|
|
/* suspend tx DMA first */
|
|
writel(D64_XC_SE, GMAC0_DMA_TX_CTRL_ADDR);
|
|
SPINWAIT(((status = (readl(GMAC0_DMA_TX_STATUS0_ADDR) &
|
|
D64_XS0_XS_MASK)) !=
|
|
D64_XS0_XS_DISABLED) &&
|
|
(status != D64_XS0_XS_IDLE) &&
|
|
(status != D64_XS0_XS_STOPPED), 10000);
|
|
|
|
/*
|
|
* PR2414 WAR: DMA engines are not disabled until
|
|
* transfer finishes
|
|
*/
|
|
writel(0, GMAC0_DMA_TX_CTRL_ADDR);
|
|
SPINWAIT(((status = (readl(GMAC0_DMA_TX_STATUS0_ADDR) &
|
|
D64_XS0_XS_MASK)) !=
|
|
D64_XS0_XS_DISABLED), 10000);
|
|
|
|
/* wait for the last transaction to complete */
|
|
udelay(2);
|
|
|
|
status = (status == D64_XS0_XS_DISABLED);
|
|
} else {
|
|
/*
|
|
* PR2414 WAR: DMA engines are not disabled until
|
|
* transfer finishes
|
|
*/
|
|
writel(0, GMAC0_DMA_RX_CTRL_ADDR);
|
|
SPINWAIT(((status = (readl(GMAC0_DMA_RX_STATUS0_ADDR) &
|
|
D64_RS0_RS_MASK)) !=
|
|
D64_RS0_RS_DISABLED), 10000);
|
|
|
|
status = (status == D64_RS0_RS_DISABLED);
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
static int gmac_enable_dma(struct eth_dma *dma, int dir)
|
|
{
|
|
uint32_t control;
|
|
|
|
debug("%s enter\n", __func__);
|
|
|
|
if (dir == MAC_DMA_TX) {
|
|
dma->cur_tx_index = 0;
|
|
|
|
/*
|
|
* These bits 20:18 (burstLen) of control register can be
|
|
* written but will take effect only if these bits are
|
|
* valid. So this will not affect previous versions
|
|
* of the DMA. They will continue to have those bits set to 0.
|
|
*/
|
|
control = readl(GMAC0_DMA_TX_CTRL_ADDR);
|
|
|
|
control |= D64_XC_XE;
|
|
if ((g_dmactrlflags & DMA_CTRL_PEN) == 0)
|
|
control |= D64_XC_PD;
|
|
|
|
writel(control, GMAC0_DMA_TX_CTRL_ADDR);
|
|
|
|
/* initailize the DMA channel */
|
|
writel((uint32_t)(dma->tx_desc_aligned),
|
|
GMAC0_DMA_TX_ADDR_LOW_ADDR);
|
|
writel(0, GMAC0_DMA_TX_ADDR_HIGH_ADDR);
|
|
} else {
|
|
dma->cur_rx_index = 0;
|
|
|
|
control = (readl(GMAC0_DMA_RX_CTRL_ADDR) &
|
|
D64_RC_AE) | D64_RC_RE;
|
|
|
|
if ((g_dmactrlflags & DMA_CTRL_PEN) == 0)
|
|
control |= D64_RC_PD;
|
|
|
|
if (g_dmactrlflags & DMA_CTRL_ROC)
|
|
control |= D64_RC_OC;
|
|
|
|
/*
|
|
* These bits 20:18 (burstLen) of control register can be
|
|
* written but will take effect only if these bits are
|
|
* valid. So this will not affect previous versions
|
|
* of the DMA. They will continue to have those bits set to 0.
|
|
*/
|
|
control &= ~D64_RC_BL_MASK;
|
|
/* Keep default Rx burstlen */
|
|
control |= readl(GMAC0_DMA_RX_CTRL_ADDR) & D64_RC_BL_MASK;
|
|
control |= HWRXOFF << D64_RC_RO_SHIFT;
|
|
|
|
writel(control, GMAC0_DMA_RX_CTRL_ADDR);
|
|
|
|
/*
|
|
* the rx descriptor ring should have
|
|
* the addresses set properly;
|
|
* set the lastdscr for the rx ring
|
|
*/
|
|
writel(((uint32_t)(dma->rx_desc_aligned) +
|
|
(RX_BUF_NUM - 1) * RX_BUF_SIZE_ALIGNED) &
|
|
D64_XP_LD_MASK, GMAC0_DMA_RX_PTR_ADDR);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
bool gmac_mii_busywait(unsigned int timeout)
|
|
{
|
|
uint32_t tmp = 0;
|
|
|
|
while (timeout > 10) {
|
|
tmp = readl(GMAC_MII_CTRL_ADDR);
|
|
if (tmp & (1 << GMAC_MII_BUSY_SHIFT)) {
|
|
udelay(10);
|
|
timeout -= 10;
|
|
} else {
|
|
break;
|
|
}
|
|
}
|
|
return tmp & (1 << GMAC_MII_BUSY_SHIFT);
|
|
}
|
|
|
|
int gmac_miiphy_read(struct mii_dev *bus, int phyaddr, int devad, int reg)
|
|
{
|
|
uint32_t tmp = 0;
|
|
u16 value = 0;
|
|
|
|
/* Busy wait timeout is 1ms */
|
|
if (gmac_mii_busywait(1000)) {
|
|
pr_err("%s: Prepare MII read: MII/MDIO busy\n", __func__);
|
|
return -1;
|
|
}
|
|
|
|
/* Read operation */
|
|
tmp = GMAC_MII_DATA_READ_CMD;
|
|
tmp |= (phyaddr << GMAC_MII_PHY_ADDR_SHIFT) |
|
|
(reg << GMAC_MII_PHY_REG_SHIFT);
|
|
debug("MII read cmd 0x%x, phy 0x%x, reg 0x%x\n", tmp, phyaddr, reg);
|
|
writel(tmp, GMAC_MII_DATA_ADDR);
|
|
|
|
if (gmac_mii_busywait(1000)) {
|
|
pr_err("%s: MII read failure: MII/MDIO busy\n", __func__);
|
|
return -1;
|
|
}
|
|
|
|
value = readl(GMAC_MII_DATA_ADDR) & 0xffff;
|
|
debug("MII read data 0x%x\n", value);
|
|
return value;
|
|
}
|
|
|
|
int gmac_miiphy_write(struct mii_dev *bus, int phyaddr, int devad, int reg,
|
|
u16 value)
|
|
{
|
|
uint32_t tmp = 0;
|
|
|
|
/* Busy wait timeout is 1ms */
|
|
if (gmac_mii_busywait(1000)) {
|
|
pr_err("%s: Prepare MII write: MII/MDIO busy\n", __func__);
|
|
return -1;
|
|
}
|
|
|
|
/* Write operation */
|
|
tmp = GMAC_MII_DATA_WRITE_CMD | (value & 0xffff);
|
|
tmp |= ((phyaddr << GMAC_MII_PHY_ADDR_SHIFT) |
|
|
(reg << GMAC_MII_PHY_REG_SHIFT));
|
|
debug("MII write cmd 0x%x, phy 0x%x, reg 0x%x, data 0x%x\n",
|
|
tmp, phyaddr, reg, value);
|
|
writel(tmp, GMAC_MII_DATA_ADDR);
|
|
|
|
if (gmac_mii_busywait(1000)) {
|
|
pr_err("%s: MII write failure: MII/MDIO busy\n", __func__);
|
|
return -1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void gmac_init_reset(void)
|
|
{
|
|
debug("%s enter\n", __func__);
|
|
|
|
/* set command config reg CC_SR */
|
|
reg32_set_bits(UNIMAC0_CMD_CFG_ADDR, CC_SR);
|
|
udelay(GMAC_RESET_DELAY);
|
|
}
|
|
|
|
void gmac_clear_reset(void)
|
|
{
|
|
debug("%s enter\n", __func__);
|
|
|
|
/* clear command config reg CC_SR */
|
|
reg32_clear_bits(UNIMAC0_CMD_CFG_ADDR, CC_SR);
|
|
udelay(GMAC_RESET_DELAY);
|
|
}
|
|
|
|
static void gmac_enable_local(bool en)
|
|
{
|
|
uint32_t cmdcfg;
|
|
|
|
debug("%s enter\n", __func__);
|
|
|
|
/* read command config reg */
|
|
cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR);
|
|
|
|
/* put mac in reset */
|
|
gmac_init_reset();
|
|
|
|
cmdcfg |= CC_SR;
|
|
|
|
/* first deassert rx_ena and tx_ena while in reset */
|
|
cmdcfg &= ~(CC_RE | CC_TE);
|
|
/* write command config reg */
|
|
writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);
|
|
|
|
/* bring mac out of reset */
|
|
gmac_clear_reset();
|
|
|
|
/* if not enable exit now */
|
|
if (!en)
|
|
return;
|
|
|
|
/* enable the mac transmit and receive paths now */
|
|
udelay(2);
|
|
cmdcfg &= ~CC_SR;
|
|
cmdcfg |= (CC_RE | CC_TE);
|
|
|
|
/* assert rx_ena and tx_ena when out of reset to enable the mac */
|
|
writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);
|
|
|
|
return;
|
|
}
|
|
|
|
int gmac_enable(void)
|
|
{
|
|
gmac_enable_local(1);
|
|
|
|
/* clear interrupts */
|
|
writel(I_INTMASK, GMAC0_INT_STATUS_ADDR);
|
|
return 0;
|
|
}
|
|
|
|
int gmac_disable(void)
|
|
{
|
|
gmac_enable_local(0);
|
|
return 0;
|
|
}
|
|
|
|
int gmac_set_speed(int speed, int duplex)
|
|
{
|
|
uint32_t cmdcfg;
|
|
uint32_t hd_ena;
|
|
uint32_t speed_cfg;
|
|
|
|
hd_ena = duplex ? 0 : CC_HD;
|
|
if (speed == 1000) {
|
|
speed_cfg = 2;
|
|
} else if (speed == 100) {
|
|
speed_cfg = 1;
|
|
} else if (speed == 10) {
|
|
speed_cfg = 0;
|
|
} else {
|
|
pr_err("%s: Invalid GMAC speed(%d)!\n", __func__, speed);
|
|
return -1;
|
|
}
|
|
|
|
cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR);
|
|
cmdcfg &= ~(CC_ES_MASK | CC_HD);
|
|
cmdcfg |= ((speed_cfg << CC_ES_SHIFT) | hd_ena);
|
|
|
|
printf("Change GMAC speed to %dMB\n", speed);
|
|
debug("GMAC speed cfg 0x%x\n", cmdcfg);
|
|
writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int gmac_set_mac_addr(unsigned char *mac)
|
|
{
|
|
/* set our local address */
|
|
debug("GMAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
|
|
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
|
|
writel(htonl(*(uint32_t *)mac), UNIMAC0_MAC_MSB_ADDR);
|
|
writew(htons(*(uint32_t *)&mac[4]), UNIMAC0_MAC_LSB_ADDR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int gmac_mac_init(struct eth_device *dev)
|
|
{
|
|
struct eth_info *eth = (struct eth_info *)(dev->priv);
|
|
struct eth_dma *dma = &(eth->dma);
|
|
|
|
uint32_t tmp;
|
|
uint32_t cmdcfg;
|
|
int chipid;
|
|
|
|
debug("%s enter\n", __func__);
|
|
|
|
/* Always use GMAC0 */
|
|
printf("Using GMAC%d\n", 0);
|
|
|
|
/* Reset AMAC0 core */
|
|
writel(0, AMAC0_IDM_RESET_ADDR);
|
|
tmp = readl(AMAC0_IO_CTRL_DIRECT_ADDR);
|
|
/* Set clock */
|
|
tmp &= ~(1 << AMAC0_IO_CTRL_CLK_250_SEL_SHIFT);
|
|
tmp |= (1 << AMAC0_IO_CTRL_GMII_MODE_SHIFT);
|
|
/* Set Tx clock */
|
|
tmp &= ~(1 << AMAC0_IO_CTRL_DEST_SYNC_MODE_EN_SHIFT);
|
|
writel(tmp, AMAC0_IO_CTRL_DIRECT_ADDR);
|
|
|
|
/* reset gmac */
|
|
/*
|
|
* As AMAC is just reset, NO need?
|
|
* set eth_data into loopback mode to ensure no rx traffic
|
|
* gmac_loopback(eth_data, TRUE);
|
|
* ET_TRACE(("%s gmac loopback\n", __func__));
|
|
* udelay(1);
|
|
*/
|
|
|
|
cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR);
|
|
cmdcfg &= ~(CC_TE | CC_RE | CC_RPI | CC_TAI | CC_HD | CC_ML |
|
|
CC_CFE | CC_RL | CC_RED | CC_PE | CC_TPI |
|
|
CC_PAD_EN | CC_PF);
|
|
cmdcfg |= (CC_PROM | CC_NLC | CC_CFE);
|
|
/* put mac in reset */
|
|
gmac_init_reset();
|
|
writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);
|
|
gmac_clear_reset();
|
|
|
|
/* enable clear MIB on read */
|
|
reg32_set_bits(GMAC0_DEV_CTRL_ADDR, DC_MROR);
|
|
/* PHY: set smi_master to drive mdc_clk */
|
|
reg32_set_bits(GMAC0_PHY_CTRL_ADDR, PC_MTE);
|
|
|
|
/* clear persistent sw intstatus */
|
|
writel(0, GMAC0_INT_STATUS_ADDR);
|
|
|
|
if (dma_init(dma) < 0) {
|
|
pr_err("%s: GMAC dma_init failed\n", __func__);
|
|
goto err_exit;
|
|
}
|
|
|
|
chipid = CHIPID;
|
|
printf("%s: Chip ID: 0x%x\n", __func__, chipid);
|
|
|
|
/* set switch bypass mode */
|
|
tmp = readl(SWITCH_GLOBAL_CONFIG_ADDR);
|
|
tmp |= (1 << CDRU_SWITCH_BYPASS_SWITCH_SHIFT);
|
|
|
|
/* Switch mode */
|
|
/* tmp &= ~(1 << CDRU_SWITCH_BYPASS_SWITCH_SHIFT); */
|
|
|
|
writel(tmp, SWITCH_GLOBAL_CONFIG_ADDR);
|
|
|
|
tmp = readl(CRMU_CHIP_IO_PAD_CONTROL_ADDR);
|
|
tmp &= ~(1 << CDRU_IOMUX_FORCE_PAD_IN_SHIFT);
|
|
writel(tmp, CRMU_CHIP_IO_PAD_CONTROL_ADDR);
|
|
|
|
/* Set MDIO to internal GPHY */
|
|
tmp = readl(GMAC_MII_CTRL_ADDR);
|
|
/* Select internal MDC/MDIO bus*/
|
|
tmp &= ~(1 << GMAC_MII_CTRL_BYP_SHIFT);
|
|
/* select MDC/MDIO connecting to on-chip internal PHYs */
|
|
tmp &= ~(1 << GMAC_MII_CTRL_EXT_SHIFT);
|
|
/*
|
|
* give bit[6:0](MDCDIV) with required divisor to set
|
|
* the MDC clock frequency, 66MHZ/0x1A=2.5MHZ
|
|
*/
|
|
tmp |= 0x1A;
|
|
|
|
writel(tmp, GMAC_MII_CTRL_ADDR);
|
|
|
|
if (gmac_mii_busywait(1000)) {
|
|
pr_err("%s: Configure MDIO: MII/MDIO busy\n", __func__);
|
|
goto err_exit;
|
|
}
|
|
|
|
/* Configure GMAC0 */
|
|
/* enable one rx interrupt per received frame */
|
|
writel(1 << GMAC0_IRL_FRAMECOUNT_SHIFT, GMAC0_INTR_RECV_LAZY_ADDR);
|
|
|
|
/* read command config reg */
|
|
cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR);
|
|
/* enable 802.3x tx flow control (honor received PAUSE frames) */
|
|
cmdcfg &= ~CC_RPI;
|
|
/* enable promiscuous mode */
|
|
cmdcfg |= CC_PROM;
|
|
/* Disable loopback mode */
|
|
cmdcfg &= ~CC_ML;
|
|
/* set the speed */
|
|
cmdcfg &= ~(CC_ES_MASK | CC_HD);
|
|
/* Set to 1Gbps and full duplex by default */
|
|
cmdcfg |= (2 << CC_ES_SHIFT);
|
|
|
|
/* put mac in reset */
|
|
gmac_init_reset();
|
|
/* write register */
|
|
writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);
|
|
/* bring mac out of reset */
|
|
gmac_clear_reset();
|
|
|
|
/* set max frame lengths; account for possible vlan tag */
|
|
writel(PKTSIZE + 32, UNIMAC0_FRM_LENGTH_ADDR);
|
|
|
|
return 0;
|
|
|
|
err_exit:
|
|
dma_deinit(dma);
|
|
return -1;
|
|
}
|
|
|
|
int gmac_add(struct eth_device *dev)
|
|
{
|
|
struct eth_info *eth = (struct eth_info *)(dev->priv);
|
|
struct eth_dma *dma = &(eth->dma);
|
|
void *tmp;
|
|
|
|
/*
|
|
* Desc has to be 16-byte aligned. But for dcache flush it must be
|
|
* aligned to ARCH_DMA_MINALIGN.
|
|
*/
|
|
tmp = memalign(ARCH_DMA_MINALIGN, DESCP_SIZE_ALIGNED * TX_BUF_NUM);
|
|
if (tmp == NULL) {
|
|
printf("%s: Failed to allocate TX desc Buffer\n", __func__);
|
|
return -1;
|
|
}
|
|
|
|
dma->tx_desc_aligned = (void *)tmp;
|
|
debug("TX Descriptor Buffer: %p; length: 0x%x\n",
|
|
dma->tx_desc_aligned, DESCP_SIZE_ALIGNED * TX_BUF_NUM);
|
|
|
|
tmp = memalign(ARCH_DMA_MINALIGN, TX_BUF_SIZE_ALIGNED * TX_BUF_NUM);
|
|
if (tmp == NULL) {
|
|
printf("%s: Failed to allocate TX Data Buffer\n", __func__);
|
|
free(dma->tx_desc_aligned);
|
|
return -1;
|
|
}
|
|
dma->tx_buf = (uint8_t *)tmp;
|
|
debug("TX Data Buffer: %p; length: 0x%x\n",
|
|
dma->tx_buf, TX_BUF_SIZE_ALIGNED * TX_BUF_NUM);
|
|
|
|
/* Desc has to be 16-byte aligned */
|
|
tmp = memalign(ARCH_DMA_MINALIGN, DESCP_SIZE_ALIGNED * RX_BUF_NUM);
|
|
if (tmp == NULL) {
|
|
printf("%s: Failed to allocate RX Descriptor\n", __func__);
|
|
free(dma->tx_desc_aligned);
|
|
free(dma->tx_buf);
|
|
return -1;
|
|
}
|
|
dma->rx_desc_aligned = (void *)tmp;
|
|
debug("RX Descriptor Buffer: %p, length: 0x%x\n",
|
|
dma->rx_desc_aligned, DESCP_SIZE_ALIGNED * RX_BUF_NUM);
|
|
|
|
tmp = memalign(ARCH_DMA_MINALIGN, RX_BUF_SIZE_ALIGNED * RX_BUF_NUM);
|
|
if (tmp == NULL) {
|
|
printf("%s: Failed to allocate RX Data Buffer\n", __func__);
|
|
free(dma->tx_desc_aligned);
|
|
free(dma->tx_buf);
|
|
free(dma->rx_desc_aligned);
|
|
return -1;
|
|
}
|
|
dma->rx_buf = (uint8_t *)tmp;
|
|
debug("RX Data Buffer: %p; length: 0x%x\n",
|
|
dma->rx_buf, RX_BUF_SIZE_ALIGNED * RX_BUF_NUM);
|
|
|
|
g_dmactrlflags = 0;
|
|
|
|
eth->phy_interface = PHY_INTERFACE_MODE_GMII;
|
|
|
|
dma->tx_packet = gmac_tx_packet;
|
|
dma->check_tx_done = gmac_check_tx_done;
|
|
|
|
dma->check_rx_done = gmac_check_rx_done;
|
|
|
|
dma->enable_dma = gmac_enable_dma;
|
|
dma->disable_dma = gmac_disable_dma;
|
|
|
|
eth->miiphy_read = gmac_miiphy_read;
|
|
eth->miiphy_write = gmac_miiphy_write;
|
|
|
|
eth->mac_init = gmac_mac_init;
|
|
eth->disable_mac = gmac_disable;
|
|
eth->enable_mac = gmac_enable;
|
|
eth->set_mac_addr = gmac_set_mac_addr;
|
|
eth->set_mac_speed = gmac_set_speed;
|
|
|
|
return 0;
|
|
}
|