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![Álvaro Fernández Rojas](/assets/img/avatar_default.png)
This patch prevents errors when running tftpput. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
649 lines
16 KiB
C
649 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* Derived from linux/drivers/dma/bcm63xx-iudma.c:
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* Copyright (C) 2015 Simon Arlott <simon@fire.lp0.eu>
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*
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* Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c:
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* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
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*
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* Derived from bcm963xx_4.12L.06B_consumer/shared/opensource/include/bcm963xx/63268_map_part.h:
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* Copyright (C) 2000-2010 Broadcom Corporation
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*
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* Derived from bcm963xx_4.12L.06B_consumer/bcmdrivers/opensource/net/enet/impl4/bcmenet.c:
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* Copyright (C) 2010 Broadcom Corporation
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dma-uclass.h>
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#include <memalign.h>
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#include <reset.h>
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#include <asm/io.h>
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#define DMA_RX_DESC 6
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#define DMA_TX_DESC 1
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/* DMA Channels */
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#define DMA_CHAN_FLOWC(x) ((x) >> 1)
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#define DMA_CHAN_MAX 16
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#define DMA_CHAN_SIZE 0x10
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#define DMA_CHAN_TOUT 500
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/* DMA Global Configuration register */
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#define DMA_CFG_REG 0x00
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#define DMA_CFG_ENABLE_SHIFT 0
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#define DMA_CFG_ENABLE_MASK (1 << DMA_CFG_ENABLE_SHIFT)
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#define DMA_CFG_FLOWC_ENABLE(x) BIT(DMA_CHAN_FLOWC(x) + 1)
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#define DMA_CFG_NCHANS_SHIFT 24
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#define DMA_CFG_NCHANS_MASK (0xf << DMA_CFG_NCHANS_SHIFT)
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/* DMA Global Flow Control registers */
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#define DMA_FLOWC_THR_LO_REG(x) (0x04 + DMA_CHAN_FLOWC(x) * 0x0c)
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#define DMA_FLOWC_THR_HI_REG(x) (0x08 + DMA_CHAN_FLOWC(x) * 0x0c)
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#define DMA_FLOWC_ALLOC_REG(x) (0x0c + DMA_CHAN_FLOWC(x) * 0x0c)
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#define DMA_FLOWC_ALLOC_FORCE_SHIFT 31
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#define DMA_FLOWC_ALLOC_FORCE_MASK (1 << DMA_FLOWC_ALLOC_FORCE_SHIFT)
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/* DMA Global Reset register */
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#define DMA_RST_REG 0x34
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#define DMA_RST_CHAN_SHIFT 0
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#define DMA_RST_CHAN_MASK(x) (1 << x)
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/* DMA Channel Configuration register */
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#define DMAC_CFG_REG(x) (DMA_CHAN_SIZE * (x) + 0x00)
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#define DMAC_CFG_ENABLE_SHIFT 0
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#define DMAC_CFG_ENABLE_MASK (1 << DMAC_CFG_ENABLE_SHIFT)
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#define DMAC_CFG_PKT_HALT_SHIFT 1
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#define DMAC_CFG_PKT_HALT_MASK (1 << DMAC_CFG_PKT_HALT_SHIFT)
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#define DMAC_CFG_BRST_HALT_SHIFT 2
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#define DMAC_CFG_BRST_HALT_MASK (1 << DMAC_CFG_BRST_HALT_SHIFT)
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/* DMA Channel Max Burst Length register */
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#define DMAC_BURST_REG(x) (DMA_CHAN_SIZE * (x) + 0x0c)
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/* DMA SRAM Descriptor Ring Start register */
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#define DMAS_RSTART_REG(x) (DMA_CHAN_SIZE * (x) + 0x00)
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/* DMA SRAM State/Bytes done/ring offset register */
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#define DMAS_STATE_DATA_REG(x) (DMA_CHAN_SIZE * (x) + 0x04)
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/* DMA SRAM Buffer Descriptor status and length register */
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#define DMAS_DESC_LEN_STATUS_REG(x) (DMA_CHAN_SIZE * (x) + 0x08)
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/* DMA SRAM Buffer Descriptor status and length register */
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#define DMAS_DESC_BASE_BUFPTR_REG(x) (DMA_CHAN_SIZE * (x) + 0x0c)
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/* DMA Descriptor Status */
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#define DMAD_ST_CRC_SHIFT 8
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#define DMAD_ST_CRC_MASK (1 << DMAD_ST_CRC_SHIFT)
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#define DMAD_ST_WRAP_SHIFT 12
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#define DMAD_ST_WRAP_MASK (1 << DMAD_ST_WRAP_SHIFT)
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#define DMAD_ST_SOP_SHIFT 13
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#define DMAD_ST_SOP_MASK (1 << DMAD_ST_SOP_SHIFT)
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#define DMAD_ST_EOP_SHIFT 14
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#define DMAD_ST_EOP_MASK (1 << DMAD_ST_EOP_SHIFT)
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#define DMAD_ST_OWN_SHIFT 15
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#define DMAD_ST_OWN_MASK (1 << DMAD_ST_OWN_SHIFT)
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#define DMAD6348_ST_OV_ERR_SHIFT 0
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#define DMAD6348_ST_OV_ERR_MASK (1 << DMAD6348_ST_OV_ERR_SHIFT)
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#define DMAD6348_ST_CRC_ERR_SHIFT 1
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#define DMAD6348_ST_CRC_ERR_MASK (1 << DMAD6348_ST_CRC_ERR_SHIFT)
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#define DMAD6348_ST_RX_ERR_SHIFT 2
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#define DMAD6348_ST_RX_ERR_MASK (1 << DMAD6348_ST_RX_ERR_SHIFT)
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#define DMAD6348_ST_OS_ERR_SHIFT 4
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#define DMAD6348_ST_OS_ERR_MASK (1 << DMAD6348_ST_OS_ERR_SHIFT)
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#define DMAD6348_ST_UN_ERR_SHIFT 9
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#define DMAD6348_ST_UN_ERR_MASK (1 << DMAD6348_ST_UN_ERR_SHIFT)
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struct bcm6348_dma_desc {
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uint16_t length;
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uint16_t status;
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uint32_t address;
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};
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struct bcm6348_chan_priv {
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void __iomem *dma_ring;
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uint8_t dma_ring_size;
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uint8_t desc_id;
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uint8_t desc_cnt;
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bool *busy_desc;
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bool running;
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};
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struct bcm6348_iudma_hw {
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uint16_t err_mask;
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};
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struct bcm6348_iudma_priv {
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const struct bcm6348_iudma_hw *hw;
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void __iomem *base;
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void __iomem *chan;
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void __iomem *sram;
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struct bcm6348_chan_priv **ch_priv;
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uint8_t n_channels;
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};
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static inline bool bcm6348_iudma_chan_is_rx(uint8_t ch)
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{
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return !(ch & 1);
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}
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static inline void bcm6348_iudma_fdc(void *ptr, ulong size)
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{
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ulong start = (ulong) ptr;
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flush_dcache_range(start, start + size);
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}
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static inline void bcm6348_iudma_idc(void *ptr, ulong size)
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{
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ulong start = (ulong) ptr;
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invalidate_dcache_range(start, start + size);
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}
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static void bcm6348_iudma_chan_stop(struct bcm6348_iudma_priv *priv,
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uint8_t ch)
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{
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unsigned int timeout = DMA_CHAN_TOUT;
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do {
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uint32_t cfg, halt;
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if (timeout > DMA_CHAN_TOUT / 2)
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halt = DMAC_CFG_PKT_HALT_MASK;
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else
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halt = DMAC_CFG_BRST_HALT_MASK;
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/* try to stop dma channel */
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writel_be(halt, priv->chan + DMAC_CFG_REG(ch));
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mb();
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/* check if channel was stopped */
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cfg = readl_be(priv->chan + DMAC_CFG_REG(ch));
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if (!(cfg & DMAC_CFG_ENABLE_MASK))
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break;
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udelay(1);
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} while (--timeout);
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if (!timeout)
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pr_err("unable to stop channel %u\n", ch);
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/* reset dma channel */
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setbits_be32(priv->base + DMA_RST_REG, DMA_RST_CHAN_MASK(ch));
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mb();
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clrbits_be32(priv->base + DMA_RST_REG, DMA_RST_CHAN_MASK(ch));
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}
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static int bcm6348_iudma_disable(struct dma *dma)
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{
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struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
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struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
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/* stop dma channel */
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bcm6348_iudma_chan_stop(priv, dma->id);
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/* dma flow control */
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if (bcm6348_iudma_chan_is_rx(dma->id))
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writel_be(DMA_FLOWC_ALLOC_FORCE_MASK,
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DMA_FLOWC_ALLOC_REG(dma->id));
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/* init channel config */
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ch_priv->running = false;
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ch_priv->desc_id = 0;
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if (bcm6348_iudma_chan_is_rx(dma->id))
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ch_priv->desc_cnt = 0;
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else
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ch_priv->desc_cnt = ch_priv->dma_ring_size;
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return 0;
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}
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static int bcm6348_iudma_enable(struct dma *dma)
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{
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const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
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struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
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struct bcm6348_dma_desc *dma_desc = ch_priv->dma_ring;
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uint8_t i;
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/* dma ring init */
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for (i = 0; i < ch_priv->desc_cnt; i++) {
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if (bcm6348_iudma_chan_is_rx(dma->id)) {
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ch_priv->busy_desc[i] = false;
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dma_desc->status |= DMAD_ST_OWN_MASK;
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} else {
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dma_desc->status = 0;
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dma_desc->length = 0;
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dma_desc->address = 0;
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}
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if (i == ch_priv->desc_cnt - 1)
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dma_desc->status |= DMAD_ST_WRAP_MASK;
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dma_desc++;
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}
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/* init to first descriptor */
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ch_priv->desc_id = 0;
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/* force cache writeback */
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bcm6348_iudma_fdc(ch_priv->dma_ring,
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sizeof(*dma_desc) * ch_priv->desc_cnt);
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/* clear sram */
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writel_be(0, priv->sram + DMAS_STATE_DATA_REG(dma->id));
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writel_be(0, priv->sram + DMAS_DESC_LEN_STATUS_REG(dma->id));
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writel_be(0, priv->sram + DMAS_DESC_BASE_BUFPTR_REG(dma->id));
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/* set dma ring start */
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writel_be(virt_to_phys(ch_priv->dma_ring),
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priv->sram + DMAS_RSTART_REG(dma->id));
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/* set flow control */
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if (bcm6348_iudma_chan_is_rx(dma->id)) {
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u32 val;
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setbits_be32(priv->base + DMA_CFG_REG,
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DMA_CFG_FLOWC_ENABLE(dma->id));
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val = ch_priv->desc_cnt / 3;
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writel_be(val, priv->base + DMA_FLOWC_THR_LO_REG(dma->id));
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val = (ch_priv->desc_cnt * 2) / 3;
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writel_be(val, priv->base + DMA_FLOWC_THR_HI_REG(dma->id));
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writel_be(0, priv->base + DMA_FLOWC_ALLOC_REG(dma->id));
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}
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/* set dma max burst */
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writel_be(ch_priv->desc_cnt,
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priv->chan + DMAC_BURST_REG(dma->id));
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/* kick rx dma channel */
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if (bcm6348_iudma_chan_is_rx(dma->id))
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setbits_be32(priv->chan + DMAC_CFG_REG(dma->id),
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DMAC_CFG_ENABLE_MASK);
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/* channel is now enabled */
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ch_priv->running = true;
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return 0;
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}
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static int bcm6348_iudma_request(struct dma *dma)
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{
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const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
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struct bcm6348_chan_priv *ch_priv;
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/* check if channel is valid */
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if (dma->id >= priv->n_channels)
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return -ENODEV;
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/* alloc channel private data */
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priv->ch_priv[dma->id] = calloc(1, sizeof(struct bcm6348_chan_priv));
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if (!priv->ch_priv[dma->id])
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return -ENOMEM;
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ch_priv = priv->ch_priv[dma->id];
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/* alloc dma ring */
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if (bcm6348_iudma_chan_is_rx(dma->id))
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ch_priv->dma_ring_size = DMA_RX_DESC;
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else
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ch_priv->dma_ring_size = DMA_TX_DESC;
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ch_priv->dma_ring =
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malloc_cache_aligned(sizeof(struct bcm6348_dma_desc) *
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ch_priv->dma_ring_size);
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if (!ch_priv->dma_ring)
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return -ENOMEM;
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/* init channel config */
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ch_priv->running = false;
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ch_priv->desc_id = 0;
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if (bcm6348_iudma_chan_is_rx(dma->id)) {
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ch_priv->desc_cnt = 0;
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ch_priv->busy_desc = calloc(ch_priv->desc_cnt, sizeof(bool));
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} else {
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ch_priv->desc_cnt = ch_priv->dma_ring_size;
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ch_priv->busy_desc = NULL;
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}
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return 0;
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}
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static int bcm6348_iudma_receive(struct dma *dma, void **dst, void *metadata)
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{
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const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
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const struct bcm6348_iudma_hw *hw = priv->hw;
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struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
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struct bcm6348_dma_desc *dma_desc = dma_desc = ch_priv->dma_ring;
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int ret;
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if (!ch_priv->running)
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return -EINVAL;
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/* get dma ring descriptor address */
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dma_desc += ch_priv->desc_id;
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/* invalidate cache data */
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bcm6348_iudma_idc(dma_desc, sizeof(*dma_desc));
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/* check dma own */
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if (dma_desc->status & DMAD_ST_OWN_MASK)
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return -EAGAIN;
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/* check pkt */
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if (!(dma_desc->status & DMAD_ST_EOP_MASK) ||
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!(dma_desc->status & DMAD_ST_SOP_MASK) ||
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(dma_desc->status & hw->err_mask)) {
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pr_err("invalid pkt received (ch=%ld desc=%u) (st=%04x)\n",
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dma->id, ch_priv->desc_id, dma_desc->status);
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ret = -EAGAIN;
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} else {
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/* set dma buffer address */
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*dst = phys_to_virt(dma_desc->address);
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/* invalidate cache data */
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bcm6348_iudma_idc(*dst, dma_desc->length);
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/* return packet length */
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ret = dma_desc->length;
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}
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/* busy dma descriptor */
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ch_priv->busy_desc[ch_priv->desc_id] = true;
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/* increment dma descriptor */
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ch_priv->desc_id = (ch_priv->desc_id + 1) % ch_priv->desc_cnt;
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return ret;
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}
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static int bcm6348_iudma_send(struct dma *dma, void *src, size_t len,
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void *metadata)
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{
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const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
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struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
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struct bcm6348_dma_desc *dma_desc;
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uint16_t status;
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if (!ch_priv->running)
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return -EINVAL;
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/* flush cache */
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bcm6348_iudma_fdc(src, len);
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/* get dma ring descriptor address */
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dma_desc = ch_priv->dma_ring;
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dma_desc += ch_priv->desc_id;
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/* config dma descriptor */
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status = (DMAD_ST_OWN_MASK |
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DMAD_ST_EOP_MASK |
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DMAD_ST_CRC_MASK |
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DMAD_ST_SOP_MASK);
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if (ch_priv->desc_id == ch_priv->desc_cnt - 1)
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status |= DMAD_ST_WRAP_MASK;
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/* set dma descriptor */
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dma_desc->address = virt_to_phys(src);
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dma_desc->length = len;
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dma_desc->status = status;
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/* flush cache */
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bcm6348_iudma_fdc(dma_desc, sizeof(*dma_desc));
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/* kick tx dma channel */
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setbits_be32(priv->chan + DMAC_CFG_REG(dma->id), DMAC_CFG_ENABLE_MASK);
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/* poll dma status */
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do {
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/* invalidate cache */
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bcm6348_iudma_idc(dma_desc, sizeof(*dma_desc));
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if (!(dma_desc->status & DMAD_ST_OWN_MASK))
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break;
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} while(1);
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/* increment dma descriptor */
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ch_priv->desc_id = (ch_priv->desc_id + 1) % ch_priv->desc_cnt;
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return 0;
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}
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static int bcm6348_iudma_free_rcv_buf(struct dma *dma, void *dst, size_t size)
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{
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const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
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struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
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struct bcm6348_dma_desc *dma_desc = ch_priv->dma_ring;
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uint16_t status;
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uint8_t i;
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u32 cfg;
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/* get dirty dma descriptor */
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for (i = 0; i < ch_priv->desc_cnt; i++) {
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if (phys_to_virt(dma_desc->address) == dst)
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break;
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dma_desc++;
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}
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/* dma descriptor not found */
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if (i == ch_priv->desc_cnt) {
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pr_err("dirty dma descriptor not found\n");
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return -ENOENT;
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}
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/* invalidate cache */
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bcm6348_iudma_idc(ch_priv->dma_ring,
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sizeof(*dma_desc) * ch_priv->desc_cnt);
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/* free dma descriptor */
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ch_priv->busy_desc[i] = false;
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status = DMAD_ST_OWN_MASK;
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if (i == ch_priv->desc_cnt - 1)
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status |= DMAD_ST_WRAP_MASK;
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dma_desc->status |= status;
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dma_desc->length = PKTSIZE_ALIGN;
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/* tell dma we allocated one buffer */
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writel_be(1, DMA_FLOWC_ALLOC_REG(dma->id));
|
|
|
|
/* flush cache */
|
|
bcm6348_iudma_fdc(ch_priv->dma_ring,
|
|
sizeof(*dma_desc) * ch_priv->desc_cnt);
|
|
|
|
/* kick rx dma channel if disabled */
|
|
cfg = readl_be(priv->chan + DMAC_CFG_REG(dma->id));
|
|
if (!(cfg & DMAC_CFG_ENABLE_MASK))
|
|
setbits_be32(priv->chan + DMAC_CFG_REG(dma->id),
|
|
DMAC_CFG_ENABLE_MASK);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bcm6348_iudma_add_rcv_buf(struct dma *dma, void *dst, size_t size)
|
|
{
|
|
const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
|
|
struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
|
|
struct bcm6348_dma_desc *dma_desc = ch_priv->dma_ring;
|
|
|
|
/* no more dma descriptors available */
|
|
if (ch_priv->desc_cnt == ch_priv->dma_ring_size) {
|
|
pr_err("max number of buffers reached\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* get next dma descriptor */
|
|
dma_desc += ch_priv->desc_cnt;
|
|
|
|
/* init dma descriptor */
|
|
dma_desc->address = virt_to_phys(dst);
|
|
dma_desc->length = size;
|
|
dma_desc->status = 0;
|
|
|
|
/* flush cache */
|
|
bcm6348_iudma_fdc(dma_desc, sizeof(*dma_desc));
|
|
|
|
/* increment dma descriptors */
|
|
ch_priv->desc_cnt++;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bcm6348_iudma_prepare_rcv_buf(struct dma *dma, void *dst,
|
|
size_t size)
|
|
{
|
|
const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
|
|
struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
|
|
|
|
/* only add new rx buffers if channel isn't running */
|
|
if (ch_priv->running)
|
|
return bcm6348_iudma_free_rcv_buf(dma, dst, size);
|
|
else
|
|
return bcm6348_iudma_add_rcv_buf(dma, dst, size);
|
|
}
|
|
|
|
static const struct dma_ops bcm6348_iudma_ops = {
|
|
.disable = bcm6348_iudma_disable,
|
|
.enable = bcm6348_iudma_enable,
|
|
.prepare_rcv_buf = bcm6348_iudma_prepare_rcv_buf,
|
|
.request = bcm6348_iudma_request,
|
|
.receive = bcm6348_iudma_receive,
|
|
.send = bcm6348_iudma_send,
|
|
};
|
|
|
|
static const struct bcm6348_iudma_hw bcm6348_hw = {
|
|
.err_mask = (DMAD6348_ST_OV_ERR_MASK |
|
|
DMAD6348_ST_CRC_ERR_MASK |
|
|
DMAD6348_ST_RX_ERR_MASK |
|
|
DMAD6348_ST_OS_ERR_MASK |
|
|
DMAD6348_ST_UN_ERR_MASK),
|
|
};
|
|
|
|
static const struct bcm6348_iudma_hw bcm6368_hw = {
|
|
.err_mask = 0,
|
|
};
|
|
|
|
static const struct udevice_id bcm6348_iudma_ids[] = {
|
|
{
|
|
.compatible = "brcm,bcm6348-iudma",
|
|
.data = (ulong)&bcm6348_hw,
|
|
}, {
|
|
.compatible = "brcm,bcm6368-iudma",
|
|
.data = (ulong)&bcm6368_hw,
|
|
}, { /* sentinel */ }
|
|
};
|
|
|
|
static int bcm6348_iudma_probe(struct udevice *dev)
|
|
{
|
|
struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev);
|
|
struct bcm6348_iudma_priv *priv = dev_get_priv(dev);
|
|
const struct bcm6348_iudma_hw *hw =
|
|
(const struct bcm6348_iudma_hw *)dev_get_driver_data(dev);
|
|
uint8_t ch;
|
|
int i;
|
|
|
|
uc_priv->supported = (DMA_SUPPORTS_DEV_TO_MEM |
|
|
DMA_SUPPORTS_MEM_TO_DEV);
|
|
priv->hw = hw;
|
|
|
|
/* dma global base address */
|
|
priv->base = dev_remap_addr_name(dev, "dma");
|
|
if (!priv->base)
|
|
return -EINVAL;
|
|
|
|
/* dma channels base address */
|
|
priv->chan = dev_remap_addr_name(dev, "dma-channels");
|
|
if (!priv->chan)
|
|
return -EINVAL;
|
|
|
|
/* dma sram base address */
|
|
priv->sram = dev_remap_addr_name(dev, "dma-sram");
|
|
if (!priv->sram)
|
|
return -EINVAL;
|
|
|
|
/* get number of channels */
|
|
priv->n_channels = dev_read_u32_default(dev, "dma-channels", 8);
|
|
if (priv->n_channels > DMA_CHAN_MAX)
|
|
return -EINVAL;
|
|
|
|
/* try to enable clocks */
|
|
for (i = 0; ; i++) {
|
|
struct clk clk;
|
|
int ret;
|
|
|
|
ret = clk_get_by_index(dev, i, &clk);
|
|
if (ret < 0)
|
|
break;
|
|
|
|
ret = clk_enable(&clk);
|
|
if (ret < 0) {
|
|
pr_err("error enabling clock %d\n", i);
|
|
return ret;
|
|
}
|
|
|
|
ret = clk_free(&clk);
|
|
if (ret < 0) {
|
|
pr_err("error freeing clock %d\n", i);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
/* try to perform resets */
|
|
for (i = 0; ; i++) {
|
|
struct reset_ctl reset;
|
|
int ret;
|
|
|
|
ret = reset_get_by_index(dev, i, &reset);
|
|
if (ret < 0)
|
|
break;
|
|
|
|
ret = reset_deassert(&reset);
|
|
if (ret < 0) {
|
|
pr_err("error deasserting reset %d\n", i);
|
|
return ret;
|
|
}
|
|
|
|
ret = reset_free(&reset);
|
|
if (ret < 0) {
|
|
pr_err("error freeing reset %d\n", i);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
/* disable dma controller */
|
|
clrbits_be32(priv->base + DMA_CFG_REG, DMA_CFG_ENABLE_MASK);
|
|
|
|
/* alloc channel private data pointers */
|
|
priv->ch_priv = calloc(priv->n_channels,
|
|
sizeof(struct bcm6348_chan_priv*));
|
|
if (!priv->ch_priv)
|
|
return -ENOMEM;
|
|
|
|
/* stop dma channels */
|
|
for (ch = 0; ch < priv->n_channels; ch++)
|
|
bcm6348_iudma_chan_stop(priv, ch);
|
|
|
|
/* enable dma controller */
|
|
setbits_be32(priv->base + DMA_CFG_REG, DMA_CFG_ENABLE_MASK);
|
|
|
|
return 0;
|
|
}
|
|
|
|
U_BOOT_DRIVER(bcm6348_iudma) = {
|
|
.name = "bcm6348_iudma",
|
|
.id = UCLASS_DMA,
|
|
.of_match = bcm6348_iudma_ids,
|
|
.ops = &bcm6348_iudma_ops,
|
|
.priv_auto_alloc_size = sizeof(struct bcm6348_iudma_priv),
|
|
.probe = bcm6348_iudma_probe,
|
|
};
|