mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-26 21:03:44 +09:00
fa85b0217d
Add copyright and license header. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
77 lines
1.7 KiB
C
77 lines
1.7 KiB
C
/*
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* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/io.h>
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#include <asm/psci.h>
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#include <asm/secure.h>
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#include <asm/arch/imx-regs.h>
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#include <common.h>
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#define GPC_CPU_PGC_SW_PDN_REQ 0xfc
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#define GPC_CPU_PGC_SW_PUP_REQ 0xf0
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#define GPC_PGC_C1 0x840
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#define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2
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/* below is for i.MX7D */
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#define SRC_GPR1_MX7D 0x074
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#define SRC_A7RCR0 0x004
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#define SRC_A7RCR1 0x008
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#define BP_SRC_A7RCR0_A7_CORE_RESET0 0
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#define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1
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static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset)
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{
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writel(enable, GPC_IPS_BASE_ADDR + offset);
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}
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__secure void imx_gpcv2_set_core1_power(bool pdn)
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{
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u32 reg = pdn ? GPC_CPU_PGC_SW_PUP_REQ : GPC_CPU_PGC_SW_PDN_REQ;
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u32 val;
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imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C1);
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val = readl(GPC_IPS_BASE_ADDR + reg);
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val |= BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7;
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writel(val, GPC_IPS_BASE_ADDR + reg);
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while ((readl(GPC_IPS_BASE_ADDR + reg) &
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BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7) != 0)
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;
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imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C1);
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}
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__secure void imx_enable_cpu_ca7(int cpu, bool enable)
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{
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u32 mask, val;
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mask = 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE + cpu - 1);
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val = readl(SRC_BASE_ADDR + SRC_A7RCR1);
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val = enable ? val | mask : val & ~mask;
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writel(val, SRC_BASE_ADDR + SRC_A7RCR1);
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}
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__secure int imx_cpu_on(int fn, int cpu, int pc)
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{
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writel(pc, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D);
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imx_gpcv2_set_core1_power(true);
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imx_enable_cpu_ca7(cpu, true);
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return 0;
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}
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__secure int imx_cpu_off(int cpu)
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{
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imx_enable_cpu_ca7(cpu, false);
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imx_gpcv2_set_core1_power(false);
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writel(0, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D + 4);
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return 0;
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}
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