mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
3d186cf3f3
A secure monitor that runs before U-Boot, and hence causes U-Boot to run in non-secure world, must implement a few operations that U-Boot otherwise implements when running in secure world. Fix U-Boot to skip these operations when running in non-secure world. In particular: - The secure monitor must provide the LP0 resume code and own LP0 configuration in order to maintain security, so must initialize all the PMC scratch registers used by the boot ROM during LP0 resume. Consequently, U-Boot should not attempt to clear those registers, since the register accesses will fail or cause an error. - The secure monitor owns system security, and so is responsible for configuring security-related items such as the VPR. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
58 lines
1.1 KiB
C
58 lines
1.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
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*/
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/* Tegra vpr routines */
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch/mc.h>
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#include <asm/arch-tegra/ap.h>
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#include <fdt_support.h>
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static bool _configured;
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void tegra_gpu_config(void)
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{
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struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
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#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
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if (!tegra_cpu_is_non_secure())
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#endif
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{
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/* Turn VPR off */
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writel(0, &mc->mc_video_protect_size_mb);
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writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED,
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&mc->mc_video_protect_reg_ctrl);
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/* read back to ensure the write went through */
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readl(&mc->mc_video_protect_reg_ctrl);
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}
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debug("configured VPR\n");
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_configured = true;
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}
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#if defined(CONFIG_OF_LIBFDT)
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int tegra_gpu_enable_node(void *blob, const char *compat)
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{
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int offset;
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if (!_configured)
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return 0;
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offset = fdt_node_offset_by_compatible(blob, -1, compat);
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while (offset != -FDT_ERR_NOTFOUND) {
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fdt_status_okay(blob, offset);
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offset = fdt_node_offset_by_compatible(blob, offset, compat);
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}
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return 0;
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}
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#endif
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