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https://github.com/brain-hackers/u-boot-brain
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60262cd041
RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
57 lines
1.4 KiB
C
57 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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*
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* RISC-V privileged architecture defined generic timer driver
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*
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* This driver relies on RISC-V platform codes to provide the essential API
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* riscv_get_time() which is supposed to return the timer counter as defined
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* by the RISC-V privileged architecture spec.
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*
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* This driver can be used in both M-mode and S-mode U-Boot.
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <timer.h>
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#include <asm/io.h>
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/**
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* riscv_get_time() - get the timer counter
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*
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* Platform codes should provide this API in order to make this driver function.
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*
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* @time: the 64-bit timer count as defined by the RISC-V privileged
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* architecture spec.
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* @return: 0 on success, -ve on error.
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*/
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extern int riscv_get_time(u64 *time);
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static int riscv_timer_get_count(struct udevice *dev, u64 *count)
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{
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return riscv_get_time(count);
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}
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static int riscv_timer_probe(struct udevice *dev)
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{
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struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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/* clock frequency was passed from the cpu driver as driver data */
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uc_priv->clock_rate = dev->driver_data;
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return 0;
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}
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static const struct timer_ops riscv_timer_ops = {
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.get_count = riscv_timer_get_count,
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};
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U_BOOT_DRIVER(riscv_timer) = {
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.name = "riscv_timer",
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.id = UCLASS_TIMER,
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.probe = riscv_timer_probe,
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.ops = &riscv_timer_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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