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https://github.com/brain-hackers/u-boot-brain
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7a2aa8b681
v7_flush_dcache_all, because it depends on omap ROM code is not generic. Rename the function to 'invalidate_dcache' and move it to the omap cpu directory. Collect the other omap cache routines l2_cache_enable and l2_cache_disable with invalide_dcache into cache.S. This means removing the old cache.c file that contained l2_cache_enable and l2_cache_disable. The conversion from cache.c to cache.S was done most through disassembling the uboot binary. The only significant change was to change the comparision for the return of get_cpu_rev from cmp r0, #0 beq earlier_than_label Which was lost information to cmp r0, #CPU_3XX_ES20 blt earlier_than_label The paths through the enable routine were verified by adding an infinite loop and seeing the hang. Then removing the infinite loop and seeing it continue. The disable routine is similar enough that it was not tested with this method. Run tested by cold booting from nand on beagle and zoom1. Compile tested on MAKEALL arm. Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
68 lines
1.8 KiB
C
68 lines
1.8 KiB
C
/*
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* (C) Copyright 2004-2008
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _SYS_PROTO_H_
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#define _SYS_PROTO_H_
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typedef struct {
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u32 mtype;
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char *board_string;
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char *nand_string;
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} omap3_sysinfo;
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void prcm_init(void);
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void per_clocks_enable(void);
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void memif_init(void);
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void sdrc_init(void);
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void do_sdrc_init(u32, u32);
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void gpmc_init(void);
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void watchdog_init(void);
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void set_muxconf_regs(void);
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u32 get_cpu_rev(void);
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u32 get_mem_type(void);
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u32 get_sysboot_value(void);
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u32 is_gpmc_muxed(void);
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u32 get_gpmc0_type(void);
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u32 get_gpmc0_width(void);
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u32 get_sdr_cs_size(u32);
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u32 get_sdr_cs_offset(u32);
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u32 is_running_in_sdram(void);
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u32 is_running_in_sram(void);
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u32 is_running_in_flash(void);
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u32 get_device_type(void);
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void l2cache_enable(void);
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void secureworld_exit(void);
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void setup_auxcr(void);
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void try_unlock_memory(void);
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u32 get_boot_type(void);
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void invalidate_dcache(u32);
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void sr32(void *, u32, u32, u32);
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u32 wait_on_value(u32, u32, void *, u32);
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void sdelay(unsigned long);
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void make_cs1_contiguous(void);
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void omap_nand_switch_ecc(int);
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void power_init_r(void);
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void dieid_num_r(void);
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#endif
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